Impact of interconnect technology scaling on SOC design methodologies

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Volumn , Issue , 2005, Pages 71-73

  Nagaraj, N S ^a   Hunter, William R ^a   Chidambaram, P R ^a   Garibay, Ty ^a   Narasimha, Usha ^a   Hill, Anthony ^a   Shichijo, Hisashi ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FILL METAL; RC DELAY; SIGNAL INTEGRITY;

EXTRACTION; FILLER METALS; RELIABILITY;

LARGE SCALE SYSTEMS;

EID: 28244498367     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Husain, A, "Models for interconnect capacitance extraction", ISQED2001,pp 167-172
2. Basel, M et al, "Parasitic extraction: current state of the art and future trends", IEEE Proceedings, Volume: 89 Issue: 5, May 2001,pp 729-739
3. Iverson, R.B et al, "A methodology for full-chip extraction of interconnect capacitance using Monte Carlo-based field solvers", SISPAD'97,pp 117-120
4. Nagaraj NS et al, "Benchmarks for Interconnect Parasitic Resistance and Capacitance" in proc. of ISQED 2003.
5. Nagaraj NS et al, "The Impact of Inductance on Transients Affecting Gate Oxide Reliability," in proc. of VLSI Design Conference, 2005.