A 10+ GHz low jitter wide band PLL in 90 nm PD SOI CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 228-231

  Boerstler, David ^a   Miki, Kazuhiko ^b   Hailu, Eskinder ^a   Kihara, Hiroki ^d   Lukes, Eric ^c   Peter, James ^a   Pettengill, Sarah ^a   Qi, Jieming ^a   Strom, James ^c   Yoshida, Munehiro ^b  

^a IBM MICROELECTRONICS   (United States)

^b Toshiba America Inc   (United States)

^c Sony Computer Entertainment Inc   (United States)

^d IBM   (United States)

Author keywords

CMOS; P P jitter; PD SOI; PLL; RMS jitter

Indexed keywords

CONTROL PATHS; FEEDFORWARD SECTIONS; RMS JITTER; VOLTAGE-CONTROLLED OSCILLATORS;

DIELECTRIC MATERIALS; ERRORS; FEEDBACK; FREQUENCIES; JITTER; LOGIC DESIGN; PHASE LOCKED LOOPS; SILICON ON INSULATOR TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 4544304166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. "A Phase-Locked Loop Clock Generator for a 1 GHz Microprocessor," D. Boerstler, and K.A. Jenkins, Digest of Technical Papers of 1998 Symposium on VLSI Circuits, 13 June 1998, Pages 212-213.
2. Boerstler, et al., US Patent 6529084
3. "Controlling Floating-Body Effects for 0.13 μm and 0.10 μm SOI CMOS," S.K.H. Fung, N. Zamdmer, P.J. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.H. Lo, R. Joshi, C.T. Chuang, I. Yang, S. Crowder, T.C. Chen, F. Assaderaghi, G. Shahidi, Technical Digest of International Electron Devices Meeting (IEDM 2000), 10-13 Dec. 2000, Pages 231-234.