BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Volumn , Issue , 2005, Pages 9-11

  Fukasawa, M ^a   Lane, S ^a   Angyal, M ^a   Chanda, K ^a   Chen, F ^a   Christiansen, C ^a   Fitzsimmons, J ^a   Gill, J ^a   Ida, K ^a   Inoue, K ^a   Kumar, K ^a   Li, B ^a   McLaughlin, P ^a   Melville, I ^a   Minami, M ^a   Nguyen, S ^a   Penny, C ^a   Sakamoto, A ^a   Shimooka, Y ^a   Ono, M ^a   McHerron, D ^a   Nogami, T ^a   Ivers, T ^a   more..

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-TO-PACKAGE (CPI); INTERCONNECT TECHNOLOGY; STRIP PROCESSES;

COPPER; ELECTRIC PROPERTIES; OPTIMIZATION; SILICON COMPOUNDS; SILICON WAFERS;

LARGE SCALE SYSTEMS;

EID: 28244489870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. Edelstein et al., Proc. IEEE IITC 2004, p. 214.
2. A. Grill et al., Proc. IEEE IITC 2004, p. 54.
3. T. Tokuyama et al., "Chou-Bisaikakou-Gijyutu" (in Japanese), p. 222.
4. M. Fukasawa et al., Proc. International Microprocesses and Nanotechnology Conference 1997, p. 186.