Defect modeling using fault tuples

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 11, 2006, Pages 2450-2464

  Blanton, R D ^a,b   Dwarakanath, Kumar N ^a,b   Desineni, Rao ^a,b  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Defect and fault modeling; Defect characterization; Diagnosis; Fault simulation; Test generation

Indexed keywords

DEFECT AND DEFAULT MODELING; DEFECT CHARACTERIZATION; FAULT SIMULATION; TEST GENERATION;

COMPUTER AIDED DIAGNOSIS; CONTROLLABILITY; DEFECTS; LOGIC PROGRAMMING; MODULATION;

INTEGRATED CIRCUITS;

EID: 33750577694     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.870836     Document Type: Article

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