Exploiting dominance and equivalence using fault tuples

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 269-274

  Dwarakanath, K N ^a   Blanton, R D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Electronic mail; Logic testing; Performance evaluation; Silicon; System testing; Virtual prototyping

Indexed keywords

BENCHMARKING; ELECTRONIC MAIL; SILICON; VIRTUAL PROTOTYPING; VLSI CIRCUITS;

BENCHMARK TESTING; CIRCUIT FAULTS; CIRCUIT TESTING; LOGIC TESTING; PERFORMANCE EVALUATION; SYSTEM TESTING;

CIRCUIT SIMULATION;

EID: 33750578662     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011151     Document Type: Conference Paper

References (9)

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