Segment delay faults: a new fault model

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 32-39

  Heragu, Keerthi ^a   Patel, Janak H ^a   Agrawal, Vishwani D ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; COMPUTER SIMULATION; DEFECTS; ERROR DETECTION; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; MATHEMATICAL MODELS; STATISTICAL METHODS;

FAULT MODEL; SEGMENT DELAY FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0029718601     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)