Universal fault simulation using fault tuples

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 786-789

  Dwarakanath, Kumar N ^a   Blanton, R D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; CONSTRAINT THEORY; DIGITAL INTEGRATED CIRCUITS; FAILURE ANALYSIS; LOGIC GATES; MATHEMATICAL MODELS; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

CENTRAL PROCESSING UNIT TIME; CLOCK CYCLE CONSTRAINT; FAULT SIMULATION; FAULT TUPLES;

INTEGRATED CIRCUIT TESTING;

EID: 0033720601     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/337292.337779     Document Type: Conference Paper

References (15)