A circuit level fault model for resistive opens and bridges

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 379-384

  Li, Zhuo ^a   Lu, Xiang ^a   Qiu, Wangqi ^a   Shi, Weiping ^a   Walker, D M H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Fault detection; Integrated circuit interconnections; Integrated circuit testing; Semiconductor device modeling; SPICE

Indexed keywords

BRIDGE CIRCUITS; CIRCUIT SIMULATION; DELAY CIRCUITS; FAULT DETECTION; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUITS; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SPICE; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; CIRCUIT-LEVEL MODELS; DELAY CALCULATION; DELAY EFFECTS; FUNCTIONAL FAULTS; INTEGRATED CIRCUIT INTERCONNECTIONS; RESISTIVE BRIDGE;

INTEGRATED CIRCUIT TESTING;

EID: 84943513961     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197678     Document Type: Conference Paper

References (14)

1. R. Rodriguez-Montanes and J. P. de Gyvez, "Resistance characterization for weak open defects", IEEE Design & Test, Sept. 2002, 18-25.
2. W. Moore, G. Gronthoud, K. Baker and M. Lousberg, "Delay-fault testing and defects in sub-micron ICs - does critical resistance really mean anything?", ITC, 2000, 95-104.
3. C. F. Hawkins, J. M. Soden, A. W. Righter, F. J. Ferguson, "Defect classes-an overdue paradigm for CMOS IC testing", ITC, 1994, 413-425.
4. S. Chakravarty, "On the capability of delay tests to detect bridges and opens", ATS, 1997, 314-319.
5. V. R. Sar-Dessai and D.M.H. Walker, "Resistive bridge fault modelling, simulation and test generation", ITC, 1999, 596-605.
6. H. Hao and E. J. McCluskey, ""Resistive shorts" within CMOS gates", ITC, 1991, 292-301.
7. M. Renovell, P. Huc and Y. Bertrand, "CMOS bridging fault modeling", VTS, 1994, 393-397.
8. M. Renovell, J. M. Galliere, F. Azais and Y. Bertrand, "Modeling gate oxide short defects in CMOS minimum transistors", European Test Workshop, 2002, 15-20.
9. W. Chuang and I N.Hajj, "Fast mixed-mode simulation for accurate MOS bridging fault detection", ISCAS, 1993, 1503-1506.
10. D. Shaw, D. Al-Khalili and C. Rozon, "Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs", ICCAD, 2001, 531-536.
11. H. T. Vierhaus, W. Meyer and U. Glaser, "CMOS bridges and resistive transistor faults: IDDQ versus delay effects", ITC, 1993, 83-91.
12. A. Krstic, Y. M. Jiang and K. T. Cheng, "Delay testing considering power supply noise effects", ITC, 1999, 181-190.
13. L. Pillage and R. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Trans. CAD, April 1990, 352-266.
14. M. Spica, M. Tripp and R. Roeder, "A new understanding of bridge defect resistances and process interactions from correlating inductive fault analysis predictions to empirical test results", IEEE Int'l Workshop on Defect Based on Testing, 2001, 11-16.