Universal test generation using fault tuples

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 812-819

  Desineni, Rao ^a   Dwarkanath, Kumar N ^a   Blanton, R D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; DATA STRUCTURES; FAILURE ANALYSIS; NAND CIRCUITS; TRANSISTORS;

FAULT TUPLES; SINGLE STUCK LINE FAULT MODEL; TRANSISTOR STUCK OPEN; UNIVERSAL TEST GENERATION;

BUILT-IN SELF TEST;

EID: 0034476396     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (22)