Efficient concurrent simulation of large networks using various fault models

Proceedings of the IEEE Annual Simulation Symposium

Volumn , Issue , 2001, Pages 51-55

  Weststrate, E ^a   Panetta, K ^a  

^a TUFTS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; FAILURE ANALYSIS; MATHEMATICAL MODELS;

CONCURRENT SIMULATION; FAULT MODELS; FAULT SIMULATION;

COMPUTER SIMULATION;

EID: 0034994981     PISSN: 02724715     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. RT-level ITC 99 benchmarks and first ATPG results
2. Probabilistic mixed-model fault diagnosis
3. Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact list
4. Fast and accurate bridging fault simulation
5. Algorithms for switch level delay fault simulation
6. A fault injection technique for VHDL behavioral-level models
7. The concurrent simulation of nearly identical networks
8. CREATOR, general and efficient multilevel concurrent simulation
9. Switch-level concurrent fault simulation based on a general purpose list traversal mechanism
10. Algorithmic aspects of symbolic switch network analysis
11. Combination profiles in sequential benchmarks for sequential test generation
12. Parallel genetic algorithms for simulation-based sequential circuit test generation