On validating data hold times for flip-flops in sequential circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 317-325

  Reddy, Sudhakar M ^a   Pomeranz, Irith ^a   Kajihara, Seiji ^b   Murakami, Atsushi ^b   Takeoka, Sadami ^c   Ohta, Mitsuyasu ^c  

^a UNIVERSITY OF IOWA   (United States)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^c PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; ERRORS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

DATA HOLD TIME; DATA SET UP TIME;

FLIP FLOP CIRCUITS;

EID: 0034482030     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2000.894220     Document Type: Article

References (8)

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