A method of test generation for path delay faults using stuck-at fault test generation algorithms

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 310-315

  Ohtake, Satoshi ^a   Ohtani, Kouhei ^b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b SANYO ELECTRIC CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; NON-ROBUST PATH; PATH DELAY FAULT; STUCK-AT FAULT TESTS; STUCK-AT FAULTS; TEST GENERATIONS; TEST PATTERN;

ALGORITHMS; EXHIBITIONS;

COMBINATORIAL CIRCUITS;

EID: 84893807320     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253625     Document Type: Conference Paper

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