New techniques for deterministic test pattern generation

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 446-452

  Hamzaoglu, I ^a   Patel, J H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; DESIGN FOR TESTABILITY; EFFICIENCY; INTEGRATED CIRCUIT TESTING; PERFORMANCE;

TEST PATTERN GENERATION;

VLSI CIRCUITS;

EID: 0032319387     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)