On the defect generation and low voltage extrapolation of QBD in SiO2/HfO2 stacks

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 140-141

  Degraeve, R ^a   Crupi, F ^b   Kwak, D H ^c   Groeseneken, G ^a,d  

^a IMEC   (Belgium)

^b UNIVERSITY OF CALABRIA   (Italy)

^c SAMSUNG Electronics   (South Korea)

^d UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DATA ACQUISITION; DIELECTRIC MATERIALS; ELECTRON ENERGY LEVELS; ELECTRON TRAPS; EXTRAPOLATION; LEAKAGE CURRENTS; MOSFET DEVICES; SILICON COMPOUNDS;

METAL GATES; STRESS-INDUCED LEAKAGE CURRENTS (SILC); TRAP DENSITY; TUNNEL CURRENTS;

HAFNIUM COMPOUNDS;

EID: 4544351365     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. Datta et al. IEDM Tech. Dig. p. 653, 2003.
2. R. Degraeve, A. Kerber et al., IEDM Tech. Dig., p. 935, 2003.
3. F. Crupi, R. Degraeve et al., to be presented IRPS 2004.
4. A. Kerber, E Cartier et al., IEEE EDL, Vol. 24, No. 2, p. 87, 2003
5. E. Cartier, A. Kerber et al. INFOS 2003.
6. G. Gellere, L. Larcher et al., Transaction Electron Dev. vol. 49, no.8, p. 1367, 2002.