-
3
-
-
33646900503
-
Device scaling limits of Si MOSFETs and their application dependencies
-
D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, H.S.P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," IEEE Proc., vol. 89, no. 3 (2001) 259-288.
-
(2001)
IEEE Proc.
, vol.89
, Issue.3
, pp. 259-288
-
-
Frank, D.J.1
Dennard, R.H.2
Nowak, E.3
Solomon, P.M.4
Taur, Y.5
Wong, H.S.P.6
-
4
-
-
0037566742
-
Frontiers of silicon-on-insulator
-
G.K. Celler and S. Cristoloveanu, "Frontiers of silicon-on- insulator", J. Appl. Phys., vol. 93 (2003) 4955-4978.
-
(2003)
J. Appl. Phys.
, vol.93
, pp. 4955-4978
-
-
Celler, G.K.1
Cristoloveanu, S.2
-
5
-
-
2042487584
-
SOI technolgy: The future will not scale down
-
Semiconductor Silicon 2002, Pennington, USA
-
S. Cristoloveanu, "SOI technolgy : the future will not scale down", Semiconductor Silicon 2002, Electrochem. Soc. Proc., vol. PV-2002-2, Pennington, USA, 2002, pp. 328-341.
-
(2002)
Electrochem. Soc. Proc.
, vol.PV-2002-2
, pp. 328-341
-
-
Cristoloveanu, S.1
-
6
-
-
0009544556
-
Ultimate MOSFETs on SOI : Ultra thin, single gate, double gate, or ground plane
-
S. Cristoloveanu, T. Ernst, D. Munteanu, and T. Ouisse, "Ultimate MOSFETs on SOI : ultra thin, single gate, double gate, or ground plane", Int. J. High Speed Electronics and Syst., vol. 10, no. 1 (2000) pp. 217-230.
-
(2000)
Int. J. High Speed Electronics and Syst.
, vol.10
, Issue.1
, pp. 217-230
-
-
Cristoloveanu, S.1
Ernst, T.2
Munteanu, D.3
Ouisse, T.4
-
7
-
-
0036498428
-
Fringing fields in sub-0.1 μm FD SOI MOSFETs: Optimization of the device architecture
-
T. Ernst, C. Tinella, and S. Cristoloveanu, "Fringing fields in sub-0.1 μm FD SOI MOSFETs: optimization of the device architecture", Solid-St. Electron., vol. 46, no. 3 (2002) pp. 373-378.
-
(2002)
Solid-st. Electron.
, vol.46
, Issue.3
, pp. 373-378
-
-
Ernst, T.1
Tinella, C.2
Cristoloveanu, S.3
-
8
-
-
0026896303
-
Scaling the Si MOSFET: From bulk to SOI to bulk
-
R-H. Yan, A. Ourmazd, and K.F. Lee, "Scaling the Si MOSFET: from bulk to SOI to bulk", IEEE Trans. Electron Devices, vol. 39, no. 7 (1992) pp. 1704-1710.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.7
, pp. 1704-1710
-
-
Yan, R.-H.1
Ourmazd, A.2
Lee, K.F.3
-
10
-
-
1542678788
-
Transition from partial to full depletion in silicon-on-insulator transistors : Impact of channel length
-
F. Allibert, J. Pretet, G. Pananakakis, S. Cristoloveanu, "Transition from partial to full depletion in silicon-on-insulator transistors : impact of channel length", Appl. Phys. Lett., vol. 84 (2004) pp. 1192-1194.
-
(2004)
Appl. Phys. Lett.
, vol.84
, pp. 1192-1194
-
-
Allibert, F.1
Pretet, J.2
Pananakakis, G.3
Cristoloveanu, S.4
-
11
-
-
0023984435
-
The voltage-doping transformation: A new approach to the modeling of MOSFET short-channel effects
-
T. Skotnicki, G. Merckel, and T. Pedron, "The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects", IEEE Electron Device Lett., vol. 9 (1988) p. 109.
-
(1988)
IEEE Electron Device Lett.
, vol.9
, pp. 109
-
-
Skotnicki, T.1
Merckel, G.2
Pedron, T.3
-
12
-
-
31844452991
-
Short-channel, narrow-channel and ultra-thin oxide effects in advanced SOI MOSFETs
-
Silicon-on-insulator Technology and Devices XII, in press, Pennington, USA
-
S. Zaouia, S. Goktepeli, A.H. Perera, and S. Cristoloveanu, "Short-channel, narrow-channel and ultra-thin oxide effects in advanced SOI MOSFETs", Silicon-on-insulator Technology and Devices XII, Electrochem. Soc. Proc., in press, Pennington, USA (2005).
-
(2005)
Electrochem. Soc. Proc.
-
-
Zaouia, S.1
Goktepeli, S.2
Perera, A.H.3
Cristoloveanu, S.4
-
13
-
-
0036838416
-
Narrow-channel effects and their impact on the static and floating-body characteristics of STI- And LOCOS- isolated SOI MOSFETs
-
J. Pretet, D. Ioannou, N. Subba, S. Cristoloveanu, W. Maszara, and C. Raynaud, "Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS- isolated SOI MOSFETs", Solid-St. Electron., vol. 46, no. 11 (2002) pp. 1699-1707.
-
(2002)
Solid-st. Electron.
, vol.46
, Issue.11
, pp. 1699-1707
-
-
Pretet, J.1
Ioannou, D.2
Subba, N.3
Cristoloveanu, S.4
Maszara, W.5
Raynaud, C.6
-
14
-
-
0026853966
-
Detailed analysis of edge effects in SIMOX MOS transistors
-
T. Elewa, B. Kleveland, S. Cristoloveanu, B. Boukriss, and A. Chovet, "Detailed analysis of edge effects in SIMOX MOS transistors", IEEE Trans. Electron Devices, vol. 39, no. 4 (1992) pp. 874-882.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.4
, pp. 874-882
-
-
Elewa, T.1
Kleveland, B.2
Cristoloveanu, S.3
Boukriss, B.4
Chovet, A.5
-
15
-
-
0033330346
-
Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFETs
-
H. Majima, H. Ishikuro, and T. Hiramoto, "Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFETs", Technical Digest IEDM'99 (1999) pp. 379-382.
-
(1999)
Technical Digest IEDM'99
, pp. 379-382
-
-
Majima, H.1
Ishikuro, H.2
Hiramoto, T.3
-
16
-
-
0020830319
-
Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs
-
H.K. Lim and J.G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs", IEEE Trans. Electron Devices, vol. 30 (1983) 1244-1251.
-
(1983)
IEEE Trans. Electron Devices
, vol.30
, pp. 1244-1251
-
-
Lim, H.K.1
Fossum, J.G.2
-
17
-
-
0442314936
-
Scaling issues for advanced SOI devices : Gate oxide tunneling, thin buried oxide, and ultra-thin films
-
Silicon Nitride and Silicon Dioxide Thin Insulating Films VII, Pennington, USA
-
J. Pretet, A. Ohata, F. Dieudonné, F. Allibert, N. Bresson, T. Matsumoto, T. Poiroux, J. Jomaah, and S. Cristoloveanu, "Scaling issues for advanced SOI devices : gate oxide tunneling, thin buried oxide, and ultra-thin films", Silicon Nitride and Silicon Dioxide Thin Insulating Films VII, Electrochem. Soc. Proc., vol. PV-2003-02, Pennington, USA, 2003, pp. 476-487.
-
(2003)
Electrochem. Soc. Proc.
, vol.PV-2003-02
, pp. 476-487
-
-
Pretet, J.1
Ohata, A.2
Dieudonné, F.3
Allibert, F.4
Bresson, N.5
Matsumoto, T.6
Poiroux, T.7
Jomaah, J.8
Cristoloveanu, S.9
-
18
-
-
0023421993
-
Double-gate silicon on insulator transistor with volume inversion: A new device with greatly enhanced performance
-
F. Balestra, S. Cristoloveanu, M. Bénachir, J. Brini, and T. Elewa, "Double-gate silicon on insulator transistor with volume inversion: a new device with greatly enhanced performance", IEEE Electron Device Lett., vol. 8, no. 9 (1987) pp. 410-412.
-
(1987)
IEEE Electron Device Lett.
, vol.8
, Issue.9
, pp. 410-412
-
-
Balestra, F.1
Cristoloveanu, S.2
Bénachir, M.3
Brini, J.4
Elewa, T.5
-
19
-
-
0038546631
-
Ultimately thin double-gate SOI MOSFETs
-
T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, "Ultimately thin double-gate SOI MOSFETs", IEEE Trans. Electron Devices, vol. 50 (2003) 830-838.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, pp. 830-838
-
-
Ernst, T.1
Cristoloveanu, S.2
Ghibaudo, G.3
Ouisse, T.4
Horiguchi, S.5
Ono, Y.6
Takahashi, Y.7
Murase, K.8
-
21
-
-
4243727848
-
Monte-Carlo simulation of electron transport in silicon-on-insulator devices
-
Silicon-On-Insulator Technology and Devices X, PV-2001-3, Pennington, USA
-
F. Gamiz, J.B. Roldan, J.A. Lopez-Villanueva, P. Cartujo-Cassinello, J.E. Carceller, and P. Cartujo, "Monte-Carlo simulation of electron transport in silicon-on-insulator devices", Silicon-On-Insulator Technology and Devices X, Electrochem. Soc. Proc., PV-2001-3, Pennington, USA, 2003, pp. 157-168.
-
(2003)
Electrochem. Soc. Proc.
, pp. 157-168
-
-
Gamiz, F.1
Roldan, J.B.2
Lopez-Villanueva, J.A.3
Cartujo-Cassinello, P.4
Carceller, J.E.5
Cartujo, P.6
-
22
-
-
17644370380
-
Mobility issues in ultra-thin SOI MOSFETs: Thickness variations, GIFBE and coupling effects
-
IEEE
-
A. Ohata, M. Cassé, S. Cristoloveanu, and T. Poiroux, "Mobility issues in ultra-thin SOI MOSFETs: thickness variations, GIFBE and coupling effects", Proc. ESSDERC 2004, IEEE (2004) pp. 109-112.
-
(2004)
Proc. ESSDERC 2004
, pp. 109-112
-
-
Ohata, A.1
Cassé, M.2
Cristoloveanu, S.3
Poiroux, T.4
-
23
-
-
20144386603
-
New magnetoresistance method for mobility extraction in scaled fully-depleted SOI devices
-
Charleston, USA
-
C. Gallon et al, "New magnetoresistance method for mobility extraction in scaled fully-depleted SOI devices", IEEE Int. SOI Conf., Charleston, USA (2004).
-
(2004)
IEEE Int. SOI Conf.
-
-
Gallon, C.1
-
24
-
-
84907704789
-
New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxide
-
Univ. of Bologna
-
J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda, and H. Brut, "New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxide", Proc. ESSDERC'02, Univ. of Bologna, 2002, pp. 515-518.
-
(2002)
Proc. ESSDERC'02
, pp. 515-518
-
-
Pretet, J.1
Matsumoto, T.2
Poiroux, T.3
Cristoloveanu, S.4
Gwoziecki, R.5
Raynaud, C.6
Roveda, A.7
Brut, H.8
-
25
-
-
0041441251
-
Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOS-FETs
-
A. Mercha, J.M. Rafi, E. Simoen, E. Augendre, and C. Claeys, "Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOS-FETs", IEEE Trans. Electron Devices, vol. 50, no. 7 (2003) 1675-1682.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.7
, pp. 1675-1682
-
-
Mercha, A.1
Rafi, J.M.2
Simoen, E.3
Augendre, E.4
Claeys, C.5
-
26
-
-
1842865577
-
Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing
-
M. Cassé, J. Pretet, S. Cristoloveanu, T. Poiroux, C. Raynaud, and G. Reimbold, "Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing", Solid-St. Electron., vol. 48, no. 7 (2004) pp. 1243-1247.
-
(2004)
Solid-st. Electron.
, vol.48
, Issue.7
, pp. 1243-1247
-
-
Cassé, M.1
Pretet, J.2
Cristoloveanu, S.3
Poiroux, T.4
Raynaud, C.5
Reimbold, G.6
-
27
-
-
1442311895
-
Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs
-
F. Dieudonné, S. Haendler, J. Jomaah, and F. Balestra, "Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs", Solid-St. Electron., vol. 48, no. 6 (2004) pp. 985-997.
-
(2004)
Solid-st. Electron.
, vol.48
, Issue.6
, pp. 985-997
-
-
Dieudonné, F.1
Haendler, S.2
Jomaah, J.3
Balestra, F.4
-
28
-
-
0030206474
-
Applications of aluminium nitride films deposited by reactive sputtering to silicon-on-insulator materials
-
S. Bengtsson, M. Bergh, M. Choumas, C. Olesen, and K.O. Jeppson, "Applications of aluminium nitride films deposited by reactive sputtering to silicon-on-insulator materials", Jpn. J. Appl. Phys., vol. 35 (1996) p. 4175-4181.
-
(1996)
Jpn. J. Appl. Phys.
, vol.35
, pp. 4175-4181
-
-
Bengtsson, S.1
Bergh, M.2
Choumas, M.3
Olesen, C.4
Jeppson, K.O.5
-
29
-
-
1442360790
-
Advanced SOI MOSFETs with buried alumina and ground plane: Self-heating and short-channel effects
-
K. Oshima, S. Cristoloveanu, B. Guillaumot, H. Iwai, and S. Deleonibus, "Advanced SOI MOSFETs with buried alumina and ground plane : self-heating and short-channel effects", Solid-St. Electron., vol. 48 (2004) pp. 907-917.
-
(2004)
Solid-st. Electron.
, vol.48
, pp. 907-917
-
-
Oshima, K.1
Cristoloveanu, S.2
Guillaumot, B.3
Iwai, H.4
Deleonibus, S.5
-
30
-
-
16244366772
-
Alter native dielectrics for advanced SOI MOSFETs: Thermal properties and short channel effects
-
Charleston, USA
-
N. Bresson, S. Cristoloveanu, K. Oshima, C. Mazure, F. Letertre, and H. Iwai, "Alter native dielectrics for advanced SOI MOSFETs : thermal properties and short channel effects", IEEE Int. SOI Conf., Charleston, USA (2004).
-
(2004)
IEEE Int. SOI Conf.
-
-
Bresson, N.1
Cristoloveanu, S.2
Oshima, K.3
Mazure, C.4
Letertre, F.5
Iwai, H.6
-
31
-
-
0037870335
-
An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode
-
D. Esseni, M. Mastrapasqua, G.K. Celler, C. Fiegna, and E. Sangiorgi, "An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode", IEEE Trans. Electron Devices, vol. 50, no. 3 (2003) 802-808.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.3
, pp. 802-808
-
-
Esseni, D.1
Mastrapasqua, M.2
Celler, G.K.3
Fiegna, C.4
Sangiorgi, E.5
-
32
-
-
28444461975
-
Total-dose radiation hardness of double-gate ultra-thin SOI MOSFETs
-
Silicon-on-Insulator Technology and Devices XI, Pennington, USA
-
C.R. Cirba, S. Cristoloveanu, R.D. Schrimpf, L.C. Feldman, D.M. Fleetwood, and K.F. Galloway, "Total-dose radiation hardness of double-gate ultra-thin SOI MOSFETs", Silicon-on-Insulator Technology and Devices XI, Electrochem. Soc. Proc. vol. 2003-05, Pennington, USA (2003) pp. 493-498.
-
(2003)
Electrochem. Soc. Proc.
, vol.2003
, Issue.5
, pp. 493-498
-
-
Cirba, C.R.1
Cristoloveanu, S.2
Schrimpf, R.D.3
Feldman, L.C.4
Fleetwood, D.M.5
Galloway, K.F.6
-
33
-
-
0032255808
-
A folded-channel MOSFET for deep-sub-tenth micron era
-
D. Hisamoto, W-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T-J. King, J. Bokor, and C. Hu, "A folded-channel MOSFET for deep-sub-tenth micron era", Technical Digest IEDM'98 (1998) pp. 1032-1034.
-
(1998)
Technical Digest IEDM'98
, pp. 1032-1034
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Anderson, E.4
Takeuchi, H.5
Asano, K.6
King, T.-J.7
Bokor, J.8
Hu, C.9
-
34
-
-
29044440093
-
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
-
D. Hisamoto, W-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T-J. King, J. Bokor, and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Devices, vol. 47, no. 12 (2000) pp. 2320-2325.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Bokor, J.9
Hu, C.10
-
35
-
-
84907562717
-
Double-gate MOSFETs: Is gate alignment mandatory?
-
Frontier Group
-
F. Allibert, A. Zaslavsky, J. Pretet and S. Cristoloveanu, "Double-gate MOSFETs: is gate alignment mandatory?", Proc. ESSDERC'2001, Frontier Group (2001) pp. 267-270.
-
(2001)
Proc. ESSDERC'2001
, pp. 267-270
-
-
Allibert, F.1
Zaslavsky, A.2
Pretet, J.3
Cristoloveanu, S.4
-
36
-
-
16244389948
-
Experimental gate misalignment analysis on double gate SOI MOSFETs
-
Charleston, USA
-
J. Widiez, F. Daugé, M. Vinet, T. Poiroux, B. Previtali, M. Mouis, and S. Deleonibus, "Experimental gate misalignment analysis on double gate SOI MOSFETs", IEEE Int. SOI Conf., Charleston, USA (2004).
-
(2004)
IEEE Int. SOI Conf.
-
-
Widiez, J.1
Daugé, F.2
Vinet, M.3
Poiroux, T.4
Previtali, B.5
Mouis, M.6
Deleonibus, S.7
-
37
-
-
5444219526
-
CMOS circuit performance enhancement by surface orientation optimization
-
L. Chang, M. Ieong, and M. Yang, "CMOS circuit performance enhancement by surface orientation optimization", IEEE Trans. Electron Devices, vol. 51, no. 10 (2004) pp. 1621-1627.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.10
, pp. 1621-1627
-
-
Chang, L.1
Ieong, M.2
Yang, M.3
-
38
-
-
0442311975
-
Coupling effects and channels separation in FinFETs
-
F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B-Y. Nguyen, "Coupling effects and channels separation in FinFETs", Solid-St. Electron., vol. 48 (2004) pp. 535-542.
-
(2004)
Solid-st. Electron.
, vol.48
, pp. 535-542
-
-
Daugé, F.1
Pretet, J.2
Cristoloveanu, S.3
Vandooren, A.4
Mathew, L.5
Jomaah, J.6
Nguyen, B.-Y.7
-
39
-
-
3943054085
-
Improvement of FinFET electrical characteristics by hydrogen annealing
-
W. Xiong, G. Gebara, J. Zaman, M. Gostkowsk, B. Nguyen, G. Smith, D. Lewis, C.R. Cleavelin, R. Wise, Y. Shaofeng, M. Pas, T-J. King, and J-P. Colinge, "Improvement of FinFET electrical characteristics by hydrogen annealing", IEEE Electron Device Lett., vol. 25, no. 8 (2004) pp. 541-543
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.8
, pp. 541-543
-
-
Xiong, W.1
Gebara, G.2
Zaman, J.3
Gostkowsk, M.4
Nguyen, B.5
Smith, G.6
Lewis, D.7
Cleavelin, C.R.8
Wise, R.9
Shaofeng, Y.10
Pas, M.11
King, T.-J.12
Colinge, J.-P.13
-
40
-
-
0347131289
-
Suppression of corner effects in triple-gate MOSFETs
-
J.G. Fossum, J.W. Yang, and V.P. Trivedi, "Suppression of corner effects in triple-gate MOSFETs", IEEE Electron Device Letters, vol. 24, no. 12 (2003) pp. 745-747.
-
(2003)
IEEE Electron Device Letters
, vol.24
, Issue.12
, pp. 745-747
-
-
Fossum, J.G.1
Yang, J.W.2
Trivedi, V.P.3
-
41
-
-
33747660475
-
The multiple-gate MOS-JFET transistor
-
World Scientific
-
B.J. Blalock, S. Cristoloveanu, B. Dufrene, F. Allibert and M.M. Mojarradi, "The multiple-gate MOS-JFET transistor", Frontiers in Electronics -Future Chips, World Scientific, vol. 26 (2002) pp. 305-314.
-
(2002)
Frontiers in Electronics - Future Chips
, vol.26
, pp. 305-314
-
-
Blalock, B.J.1
Cristoloveanu, S.2
Dufrene, B.3
Allibert, F.4
Mojarradi, M.M.5
-
42
-
-
84907695668
-
4-FETs
-
Lisbon
-
4-FETs", Proc. ESSDERC'03, Lisbon (2003) pp. 127-130.
-
(2003)
Proc. ESSDERC'03
, pp. 127-130
-
-
Akarvardar, K.1
Dufrene, B.2
Cristoloveanu, S.3
Blalock, B.4
Higashino, T.5
Mojarradi, M.6
Kolawa, E.7
|