Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing

Solid-State Electronics

Volumn 48, Issue 7, 2004, Pages 1243-1247

  Casse M ^a   Pretet, J ^b,c   Cristoloveanu, S ^b   Poiroux, T ^a   Fenouillet Beranger, C ^a   Fruleux, F ^c   Raynaud, C ^a   Reimbold, G ^a  

^a CEA LETI   (France)

^b IMEP LAHC   (France)

^c STMICROELECTRONICS   (France)

Author keywords

Floating body effect; Silicon on insulator (SOI) MOSFET; Tunneling

Indexed keywords

BAND STRUCTURE; CHARGE CARRIERS; ELECTRIC FIELDS; ELECTRON TUNNELING; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

FLOATING-BODY EFFECTS; SILICON-ON-INSULATOR (SOI) MOSFET;

MOSFET DEVICES;

EID: 1842865577     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.01.002     Document Type: Article

References (10)

1. Frank D.J., Dennard R.H., Nowak E., Solomon P.M., Taur Y., Wong H.S.P. Device scaling limits of Si MOSFETs and their application dependencies. IEEE Proc. 89(3):2001;259-288.
2. Cristoloveanu S., Li S.S. Electrical characterization of silicon-on-insulator materials and devices. 1995;Kluwer Academic Publishers.
3. Colinge J.P. Silicon-on-insulator technology: materials to VLSI. 1991;Kluwer Academic Publishers.
4. Pretet J, Matsumoto T, Poiroux T, Cristoloveanu S, Gwoziecki R, Raynaud C, et al. New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxides. In: Proc ESSDERC, September 2002. p. 515.
5. Poiroux T, Faynot O, Tabone C, Tigelaar H, Mogul H, Bresson N, et al. Emerging floating-body effects in advanced partially-depleted SOI devices. In: IEEE Int SOI Conf Proc, October 2002. p. 99-100.
6. Dieudonne F, Haendler S, Jomaah J, Raynaud C, De Meyer K, Van Meer H, et al. Shrinking from 0.25 down to 0.12 μm SOI CMOS technology node: a contribution to 1/f noise in partially depleted N-MOSFETs. In: Proc 3rd European Workshop on Ultimate Integration of Silicon, 2002. p. 33.
7. Fossum J.G., Krishnan S., Faynot O., Cristoloveanu S., Raynaud C. Subthreshold kinks in fully depleted SOI MOSFET's. IEEE Eletron Dev. Lett. 16(12):1995;542-544.
8. Lim H.K., Fossum J.G. Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's. IEEE Trans. Electron Dev. 30(10):1983;1244-1251.
9. Pretet J., Subba N., Ioannou D., Cristoloveanu S., Maszara W., Raynaud C. Narrow channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs. Solid-state Electron. 46:2002;1699-1707.
10. Munteanu D., Weiser D.A., Cristoloveanu S., Faynot O., Pelloie J.-L., Fossum J.G. Generation/recombination transient effects in partially depleted SOI transisors: systematic experiments and simulations. IEEE Trans. Electron Dev. 45(8):1998;1678-1683.