-
1
-
-
0036923554
-
Extreme scaling with ultrathin Si channel MOSFETs
-
Dec.
-
B. Doris, M. Ieong, T. Kanarsky, Y. Zing, R. A. Roy, O. Dokumaci, Z. Ren, F.-F Jamin, L. Shi, W. Natzle, H.-J Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S P. Wong, and W. Haensch, "Extreme scaling with ultrathin Si channel MOSFETs," in IEDM Tech. Dig., Dec. 2002, pp. 267-270.
-
(2002)
IEDM Tech. Dig.
, pp. 267-270
-
-
Doris, B.1
Ieong, M.2
Kanarsky, T.3
Zing, Y.4
Roy, R.A.5
Dokumaci, O.6
Ren, Z.7
Jamin, F.-F.8
Shi, L.9
Natzle, W.10
Huang, H.-J.11
Mezzapelle, J.12
Mocuta, A.13
Womack, S.14
Gribelyuk, M.15
Jones, E.C.16
Miller, R.J.17
Wong, H.-S.P.18
Haensch, W.19
-
2
-
-
0035250378
-
Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
-
Feb.
-
K. Kim and J. G. Possum, "Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 294-299
-
-
Kim, K.1
Possum, J.G.2
-
3
-
-
0033329310
-
Sub-50 nm FinFET: PMOS
-
Dec.
-
X. Huang, W.-C Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K Choi, K. Asano, V. Subramanian, T.-J King, J. Bokor, and C. Hu. "Sub-50 nm FinFET: PMOS," in IEDM Tech. Dig., Dec. 1999, pp. 67-70.
-
(1999)
IEDM Tech. Dig.
, pp. 67-70
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
Subramanian, V.11
King, T.-J.12
Bokor, J.13
Hu, C.14
-
5
-
-
0037646045
-
Advanced depicted-substrate transistors: Single-gate, double-gate, and tri-gate
-
Sept.
-
R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Mutiny, M. Doczy, R. Rios, T. Union, R. Arghavani, B. Jin, S. Datta, and S. Hareland, "Advanced depicted-substrate transistors: Single-gate, double-gate, and tri-gate," in Proc. Int. Conf. Solid State Devices and Materials, Sept. 2002. pp. 68-69.
-
(2002)
Proc. Int. Conf. Solid State Devices and Materials
, pp. 68-69
-
-
Chau, R.1
Doyle, B.2
Kavalieros, J.3
Barlage, D.4
Mutiny, A.5
Doczy, M.6
Rios, R.7
Union, T.8
Arghavani, R.9
Jin, B.10
Datta, S.11
Hareland, S.12
-
6
-
-
0141761518
-
Tri-gate fully depleted CMOS transistors: Fabrication, design, and layout
-
June
-
B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Tri-gate fully depleted CMOS transistors: Fabrication, design, and layout," in Proc. VLSI Tech. Symp., June 2003, pp. 133-134.
-
(2003)
Proc. VLSI Tech. Symp.
, pp. 133-134
-
-
Doyle, B.1
Boyanov, B.2
Datta, S.3
Doczy, M.4
Hareland, S.5
Jin, B.6
Kavalieros, J.7
Linton, T.8
Rios, R.9
Chau, R.10
-
7
-
-
0346998221
-
-
Synopsys, Inc., Durham, NC
-
MEDICI-4.0 Users Manual, Synopsys, Inc., Durham, NC, 2002.
-
(2002)
MEDICI-4.0 Users Manual
-
-
-
8
-
-
0036475197
-
Analytical modeling of quantization and volume inversion in thin Si-film double-gate MOSFETs
-
Feb.
-
L. Ge and J. G. Possum, "Analytical modeling of quantization and volume inversion in thin Si-film double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 287-294, Feb. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 287-294
-
-
Ge, L.1
Possum, J.G.2
-
9
-
-
0020830319
-
Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETS
-
Oct.
-
H.-K. Lim and J. G. Possum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETS," IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, pp. 1244-1251
-
-
Lim, H.-K.1
Possum, J.G.2
|