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Volumn 50, Issue 7, 2003, Pages 1675-1682

"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs

Author keywords

Floating body effects; Generation lifetime; Kink effect; Lorentzian noise spectrum; Noise overshoot; Switch off transient; Transconductance peak

Indexed keywords

BAND STRUCTURE; CRYOGENICS; ELECTRON TUNNELING; GATES (TRANSISTOR); IMPACT IONIZATION; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; TRANSCONDUCTANCE; TRANSIENTS; ULTRATHIN FILMS;

EID: 0041441251     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.814983     Document Type: Article
Times cited : (129)

References (18)
  • 1
    • 0024870229 scopus 로고
    • A re-examination of the physics of multiplication-induced breakdown in MOSFETs
    • Dec.
    • T. Skotnicki, G. Merckel, and A. Merrachi, "A re-examination of the physics of multiplication-induced breakdown in MOSFETs," in IEDM Tech. Dig., Dec. 1989, pp. 87-90.
    • (1989) IEDM Tech. Dig. , pp. 87-90
    • Skotnicki, T.1    Merckel, G.2    Merrachi, A.3
  • 2
    • 0029490216 scopus 로고
    • Monte carlo study of sub-band-gap impact ionization in small silicon field-effect transistors
    • Dec.
    • M. V. Fischetti and S. E. Laux, "Monte carlo study of sub-band-gap impact ionization in small silicon field-effect transistors," in IEDM Tech. Dig., Dec. 1995, pp. 305-308.
    • (1995) IEDM Tech. Dig. , pp. 305-308
    • Fischetti, M.V.1    Laux, S.E.2
  • 3
    • 0034454472 scopus 로고    scopus 로고
    • Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFET's
    • Dec.
    • K. G. Anil, S. Mahapatra, and I. Eisele, "Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFET's," in IEDM Tech. Dig., Dec. 2000, pp. 675-678.
    • (2000) IEDM Tech. Dig. , pp. 675-678
    • Anil, K.G.1    Mahapatra, S.2    Eisele, I.3
  • 4
    • 0003136914 scopus 로고    scopus 로고
    • Improved LOCOS isolation for ultra thin 0.18 μm fully-depleted SOI CMOS
    • The Electrochem. Soc. Proc., S. Cristoloveanu, G. K. Celler, P. L. F. Hemment, F. Assaderaghi, K. T. Izumi, and Y.-W. Kim, Eds., Pennington, NJ
    • H. van Meer and K. De Meyer, "Improved LOCOS isolation for ultra thin 0.18 μm fully-depleted SOI CMOS," in Proc. 10th Int. Symp. Silicon-on-Insulator Technology Devices X, vol. 2001-3, The Electrochem. Soc. Proc., S. Cristoloveanu, G. K. Celler, P. L. F. Hemment, F. Assaderaghi, K. T. Izumi, and Y.-W. Kim, Eds., Pennington, NJ, 2001, pp. 301-303.
    • (2001) Proc. 10th Int. Symp. Silicon-on-Insulator Technology Devices X , vol.2001-2003 , pp. 301-303
    • Van Meer, H.1    De Meyer, K.2
  • 5
    • 0033324935 scopus 로고    scopus 로고
    • Extraction of the gate oxide thickness of N- and P-channel MOSFET's below 20 Å from the substrate current resulting from valence-band electron tunneling
    • Dec.
    • A. Shanware, J. P. Shiely, H. Z. Massoud, E. Vogel, K. Henson, A. Srivastava, C. Osburn, J. R. Hauser, and J. J. Wortman, "Extraction of the gate oxide thickness of N- and P-channel MOSFET's below 20 Å from the substrate current resulting from valence-band electron tunneling," in IEDM Tech. Dig., Dec. 1999, pp. 815-818.
    • (1999) IEDM Tech. Dig. , pp. 815-818
    • Shanware, A.1    Shiely, J.P.2    Massoud, H.Z.3    Vogel, E.4    Henson, K.5    Srivastava, A.6    Osburn, C.7    Hauser, J.R.8    Wortman, J.J.9
  • 6
    • 0035395857 scopus 로고    scopus 로고
    • Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction and valence band electron and hole tunneling
    • July
    • W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction and valence band electron and hole tunneling," IEEE Trans. Electron Devices, vol. 48, pp. 1366-1373, July 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , pp. 1366-1373
    • Lee, W.-C.1    Hu, C.2
  • 7
    • 0036564062 scopus 로고    scopus 로고
    • Parasitic conduction in a 0.13-μm CMOS technology at low temperature
    • J. de Physique IV, F. Balestra, Ed., Grenoble, France, June 17-20
    • A. Mercha, J. M. Rafí, E. Augendre, E. Simoen, and C. Claeys, "Parasitic conduction in a 0.13-μm CMOS technology at low temperature," in Proc. WOLTE 5, vol. 12, J. de Physique IV, F. Balestra, Ed., Grenoble, France, June 17-20, 2002, pp. Pr3-61-Pr3-65.
    • (2002) Proc. WOLTE 5 , vol.12
    • Mercha, A.1    Rafí, J.M.2    Augendre, E.3    Simoen, E.4    Claeys, C.5
  • 8
    • 84907704789 scopus 로고    scopus 로고
    • New mechanism of body charging in partially depleted SOI-MOSFET's with ultra-thin gate oxides
    • G. Baccarani, E. Gnani, and M. Rudan, Eds., Italy, Sept.
    • J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda, and H. Brut, "New mechanism of body charging in partially depleted SOI-MOSFET's with ultra-thin gate oxides," in Proc. ESSDERC, G. Baccarani, E. Gnani, and M. Rudan, Eds., Italy, Sept. 2002, pp. 515-518.
    • (2002) Proc. ESSDERC , pp. 515-518
    • Pretet, J.1    Matsumoto, T.2    Poiroux, T.3    Cristoloveanu, S.4    Gwoziecki, R.5    Raynaud, C.6    Roveda, A.7    Brut, H.8
  • 9
    • 0026172140 scopus 로고
    • The importance of the internal bulk-source potential on the low temperature kink in NMOST's
    • June
    • L. Deferm, E. Simoen, and C. Claeys, "The importance of the internal bulk-source potential on the low temperature kink in NMOST's," IEEE Trans. Electron Devices, vol. 38, pp. 1459-1466, June 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 1459-1466
    • Deferm, L.1    Simoen, E.2    Claeys, C.3
  • 10
    • 20244388081 scopus 로고    scopus 로고
    • Carrier recombination and thin gate oxide effects in floating body SOI MOSFETs: Influence of the device geometries and architectures
    • Oct.
    • J. Pretet, T. Matsumoto, R. Gwoziecki, C. Raynaud, S. Cristoloveanu, T. Poiroux, and H. Brut, "Carrier recombination and thin gate oxide effects in floating body SOI MOSFETs: Influence of the device geometries and architectures," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 101-102.
    • (2002) Proc. IEEE Int. SOI Conf. , pp. 101-102
    • Pretet, J.1    Matsumoto, T.2    Gwoziecki, R.3    Raynaud, C.4    Cristoloveanu, S.5    Poiroux, T.6    Brut, H.7
  • 11
    • 0037451258 scopus 로고    scopus 로고
    • Low frequency noise overshoot in ultra thin gate oxide silicon on insulator metal oxide semiconductor field effect transistors
    • Mar.
    • A. Mercha, E. Simoen, H. V. Meer, and C. Claeys, "Low frequency noise overshoot in ultra thin gate oxide silicon on insulator metal oxide semiconductor field effect transistors," Appl. Phys. Lett., vol. 82, pp. 1790-1792, Mar. 2003.
    • (2003) Appl. Phys. Lett. , vol.82 , pp. 1790-1792
    • Mercha, A.1    Simoen, E.2    Meer, H.V.3    Claeys, C.4
  • 12
    • 0028397668 scopus 로고
    • The kink-related excess low-frequency noise in silicon-on-insulator MOST's
    • May
    • E. Simoen, U. Magnusson, A. L. P. Rotondaro, and C. Claeys, "The kink-related excess low-frequency noise in silicon-on-insulator MOST's," IEEE Trans. Electron Devices, vol. 41, pp. 330-339, May 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , pp. 330-339
    • Simoen, E.1    Magnusson, U.2    Rotondaro, A.L.P.3    Claeys, C.4
  • 13
    • 0035395568 scopus 로고    scopus 로고
    • Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFET's and device design optimization for RFICs
    • July
    • Y.-C. Tseng, W. M. Huang, M. Mendicino, D. J. Monk, P. J. Welch, and J. C. S. Woo, "Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFET's and device design optimization for RFICs," IEEE Trans. Electron Devices, vol. 48, pp. 1428-1437, July 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , pp. 1428-1437
    • Tseng, Y.-C.1    Huang, W.M.2    Mendicino, M.3    Monk, D.J.4    Welch, P.J.5    Woo, J.C.S.6
  • 14
    • 0033750499 scopus 로고    scopus 로고
    • Physical noise modeling of SOI MOSFET's with analysis of the Lorentzian component in the low-frequency noise spectrum
    • June
    • G. O., Workman and J. G. Fossum, "Physical noise modeling of SOI MOSFET's with analysis of the Lorentzian component in the low-frequency noise spectrum," IEEE Trans. Electron Devices, vol. 47, pp. 1192-1201, June 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , pp. 1192-1201
    • Workman, G.O.1    Fossum, J.G.2
  • 15
    • 0036637862 scopus 로고    scopus 로고
    • SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250°C
    • July
    • V.Dessard, B. Iníguez, S. Adriaensen, and D. Flandre, "SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250°C," IEEE Trans. Electron Devices, vol. 49, pp. 1289-1295, July 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , pp. 1289-1295
    • Dessard, V.1    Iníguez, B.2    Adriaensen, S.3    Flandre, D.4
  • 17
    • 0003640512 scopus 로고    scopus 로고
    • On the noise in dynamic threshold (DT) MOS/SOI transistors
    • Cork, Ireland, Sept.
    • S. Haendler, J. Jomaah, F. Balestra, and J. L. Pelloie, "On the noise in dynamic threshold (DT) MOS/SOI transistors," in Proc. ESSDERC, Cork, Ireland, Sept. 2000, pp. 504-507.
    • (2000) Proc. ESSDERC , pp. 504-507
    • Haendler, S.1    Jomaah, J.2    Balestra, F.3    Pelloie, J.L.4
  • 18
    • 0036575333 scopus 로고    scopus 로고
    • Principles of transient charge pumping on partially depleted SOI MOSFET's
    • May
    • S. Okhonin, M. Nagoga, and P. Fazan, "Principles of transient charge pumping on partially depleted SOI MOSFET's," IEEE Electron Device Lett., vol. 23, pp. 279-281, May 2002.
    • (2002) IEEE Electron Device Lett. , vol.23 , pp. 279-281
    • Okhonin, S.1    Nagoga, M.2    Fazan, P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.