Integrated simulation of Line-Edge Roughness (LER) effects on Sub-65 nm transistor operation: From lithography simulation, to LER metrology, to device operation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6151 II, Issue , 2006, Pages

  Patsis, G P ^a   Constantoudis, V ^a   Gogolides, E ^a  

^a INSTITUTE OF MICROELECTRONICS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LITHOGRAPHY; MOS DEVICES; THRESHOLD VOLTAGE; TRANSISTORS;

LINE-EDGE ROUGHNESS (LER); SELF-AFFINE CHARACTERISTICS; THRESHOLD VOLTAGE SHIFTS; TRANSISTOR GATES;

SURFACE ROUGHNESS;

EID: 33745588529     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.654736     Document Type: Conference Paper

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