Metrology of LER: Influence of line-edge roughness (LER) on transistor performance

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5375, Issue PART 1, 2004, Pages 468-476

  Yamaguchi, Atsuko ^a   Ichinose, Katsuhiko ^a   Shimamoto, Satoshi ^a   Fukuda, Hiroshi ^a   Tsuchiya, Ryuta ^a   Ohnishi, Kazuhiro ^a,c   Kawada, Hiroki ^b   Iizumi, Takashi ^b  

^a HITACHI LTD   (Japan)

^b HITACHI HIGH TECHNOLOGIES CORPORATION   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

CD SEM; Line edge roughness; Metrology; Transistor performance

Indexed keywords

CD-SEM; LINE-EDGE ROUGHNESS (LER); TRANSISTOR PERFORMANCE;

COMPUTER SIMULATION; ERROR ANALYSIS; LITHOGRAPHY; LSI CIRCUITS; OPTICAL FIBER FABRICATION; SURFACE ROUGHNESS;

TRANSISTORS;

EID: 4344603151     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.534631     Document Type: Conference Paper

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