Effect of line edge roughness (LER) and line width roughness (LWR) on sub-100 nm device performance

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5376, Issue PART 1, 2004, Pages 426-433

  Lee, Ji Young ^a   Shin, Jangho ^a   Kim, Hyun Woo ^a   Woo, Sang Gyun ^a   Cho, Han Ku ^a   Han, Woo Sung ^a   Moon, Joo Tae ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

ArF; Leakage current; LER; LWR; Threshold Voltage Variation; Transistor performance degradation

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ETCHING; LEAKAGE CURRENTS; PHOTORESISTS; THIN FILMS; THRESHOLD VOLTAGE; TRANSISTORS;

ARF; LINE EDGE ROUGHNESS (LER); LINE WIDTH ROUGHNESS (LWR); THRESHOLD VOLTAGE VARIATION; TRANSISTOR PERFORMANCE DEGRADATION;

SEMICONDUCTOR DEVICES;

EID: 3843130605     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.534926     Document Type: Conference Paper

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