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1
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0036928972
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Determination of the line edge roughness specification for 34 nm devices
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session 12-1
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T. Linton, M. Candhok, B. J. Rice, and G. Schrom, "Determination of the line edge roughness specification for 34 nm devices", Technical Digest of IEDM, session 12-1, 2002.
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(2002)
Technical Digest of IEDM
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Linton, T.1
Candhok, M.2
Rice, B.J.3
Schrom, G.4
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2
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0036927513
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Line edge roughness: Characterization, modeling and impact on device behavior
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session 12-2
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J. A. Croon, G Storms, S. Winkelmeier, I. Pollentier, M. Ercken, S. Decoutere, W. Sansen, and H. E. Maes, "Line edge roughness: characterization, modeling and impact on device behavior", Technical Digest of IEDM, session 12-2, 2002.
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(2002)
Technical Digest of IEDM
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Croon, J.A.1
Storms, G.2
Winkelmeier, S.3
Pollentier, I.4
Ercken, M.5
Decoutere, S.6
Sansen, W.7
Maes, H.E.8
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3
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0042532317
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Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
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A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness", Trans. on Electron devices, vol. 50, no. 5, pp 1254-1260, 2003.
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(2003)
Trans. on Electron Devices
, vol.50
, Issue.5
, pp. 1254-1260
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Asenov, A.1
Kaya, S.2
Brown, A.R.3
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4
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0842331392
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Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects
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session 9-5
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M. Hane, T. Ikezawa, and T. Ezaki, "Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects", Technical Digest of IEDM, session 9-5, 2003.
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(2003)
Technical Digest of IEDM
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Hane, M.1
Ikezawa, T.2
Ezaki, T.3
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5
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0035364688
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An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
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C. H. Diaz, H. J. Tao, Y. C. Ku, A. Yen, and K. Young, "An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling", Electron Device Letters, vol. 22, no. 6, pp. 287-289, 2001.
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(2001)
Electron Device Letters
, vol.22
, Issue.6
, pp. 287-289
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Diaz, C.H.1
Tao, H.J.2
Ku, Y.C.3
Yen, A.4
Young, K.5
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6
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0035982537
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Study of the acid-diffusion effect on line edge roughness using the edge roughness evaluation method
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M. Yoshizawa, and S. Moriya, "Study of the acid-diffusion effect on line edge roughness using the edge roughness evaluation method", J. Vac. Sci. Technol. B, vol. 20, no. 4, pp. 1342-1347, 2002.
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(2002)
J. Vac. Sci. Technol. B
, vol.20
, Issue.4
, pp. 1342-1347
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Yoshizawa, M.1
Moriya, S.2
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7
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0038506917
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Advanced resist design using AFM analysis for ArF lithography
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N. Kubota, T. Hayashi, T. Iwai, H. Komano, and A.Kawai, "Advanced resist design using AFM analysis for ArF lithography", J. Photopolym. Sci. Technol., vol. 16, no. 3, pp. 467-473, 2003.
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(2003)
J. Photopolym. Sci. Technol.
, vol.16
, Issue.3
, pp. 467-473
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Kubota, N.1
Hayashi, T.2
Iwai, T.3
Komano, H.4
Kawai, A.5
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8
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33745617811
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Line edge roughness in sub-0.18μm resist patterns
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S. Palmateer, S. Cann, J. Curtin, S. Doran, L. Eriksen, A. Forte, R. Kunz, T. Lyszczarz, and M. Stern, "Line edge roughness in sub-0.18μm resist patterns", Proc. SPIE, vol. 3333, pp. 634-642, 1998.
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(1998)
Proc. SPIE
, vol.3333
, pp. 634-642
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Palmateer, S.1
Cann, S.2
Curtin, J.3
Doran, S.4
Eriksen, L.5
Forte, A.6
Kunz, R.7
Lyszczarz, T.8
Stern, M.9
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9
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0141608680
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Characterization of line-edge roughness in resist patterns and estimation of its effect on device performance
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A. Yamaguchi, R. Tsuchiya, H. Fukuda, O. Komuro, H. Kawada, and T. Iizumi, "Characterization of line-edge roughness in resist patterns and estimation of its effect on device performance", Proc. SPIE, vol. 5038, pp. 689-698, 2003.
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(2003)
Proc. SPIE
, vol.5038
, pp. 689-698
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Yamaguchi, A.1
Tsuchiya, R.2
Fukuda, H.3
Komuro, O.4
Kawada, H.5
Iizumi, T.6
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10
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4344711901
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Evaluation of transistor property variations within chips on 300 nm wafers using a new MOSFET array test structure
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N. Izumi, H. Ozaki, Y. Nakagawa, N. Kasai, M. yasuhira, and T. Arikado, "Evaluation of transistor property variations within chips on 300 nm wafers using a new MOSFET array test structure", Proc. ISSM, pp. 91-94, 2003.
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(2003)
Proc. ISSM
, pp. 91-94
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Izumi, N.1
Ozaki, H.2
Nakagawa, Y.3
Kasai, N.4
Yasuhira, M.5
Arikado, T.6
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11
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0035450052
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Metrology method for the correlation of line edge roughness for different resists before and after etch
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S. Winkelmeier, M. Sarstedt, M. Ereken, M. Goethals, and K. Ronse, "Metrology method for the correlation of line edge roughness for different resists before and after etch", Microelectronic Engineering, pp. 665-672, 2001.
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(2001)
Microelectronic Engineering
, pp. 665-672
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Winkelmeier, S.1
Sarstedt, M.2
Ereken, M.3
Goethals, M.4
Ronse, K.5
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12
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0041361764
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Characterization of line edge roughness in resist patterns by using Fourier analysis and auto-correlation function
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A. Yamaguchi, and O. Komuro, "Characterization of line edge roughness in resist patterns by using Fourier analysis and auto-correlation function", Jpn. J. Appl. Phys. vol. 42, no. 6B, pp. 3763-3770, 2003.
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(2003)
Jpn. J. Appl. Phys.
, vol.42
, Issue.6 B
, pp. 3763-3770
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Yamaguchi, A.1
Komuro, O.2
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13
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0038457081
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Quantification of line-edge roughness of photoresists. 2. Scaling and fractal analysis and the best roughness descriptors
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V.Constantoudis, G.P. Patsis, A. Tserepi, and E. Gogolides, "Quantification of line-edge roughness of photoresists. 2. Scaling and fractal analysis and the best roughness descriptors", J. Vac. Sci. Technol. B, vol. 21, no. 3, pp. 1019-1026, 2003.
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(2003)
J. Vac. Sci. Technol. B
, vol.21
, Issue.3
, pp. 1019-1026
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Constantoudis, V.1
Patsis, G.P.2
Tserepi, A.3
Gogolides, E.4
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