Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 73-76

  Ge, C H ^a   Lin, C C ^a   Ko, C H ^a   Huang, C C ^a   Huang, Y C ^a   Chan, B W ^a   Perng, B C ^a   Sheu, C C ^a   Tsai, P Y ^a   Yao, L G ^a   Wu, C L ^a   Lee, T L ^a   Chen, C J ^a   Wang, C T ^a   Lin, S C ^a   Yeo, Y C ^a   Hu, C ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSIVE STRESS; COST EFFECTIVENESS; ION IMPLANTATION; MOSFET DEVICES; SILICON COMPOUNDS; STRAIN; TENSILE STRESS;

PROCESS STRAINED SILICON (PSS); STRAIN ENGINEERING;

CMOS INTEGRATED CIRCUITS;

EID: 0842288292     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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