Modular SOC testing with reduced wrapper count

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 12, 2005, Pages 1894-1908

  Xu, Qiang ^a,b   Nicolici, Nicola ^a,c,d,e  

^a IEEE   (United States)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^c MCMASTER UNIVERSITY   (Canada)

^d ASSOCIATION FOR COMPUTING MACHINERY   (United States)

^e IEEE Circuits and Systems Societies ^*  (Canada)

Author keywords

Core wrapper; Electronic test; System on a chip (SOC)

Indexed keywords

CORE WRAPPER; DESIGN ALGORITHM; ELECTRONIC TEST; SYSTEM-ON-A-CHIP (SOC);

ALGORITHMS; COMPUTER ARCHITECTURE; ELECTRONIC EQUIPMENT TESTING; PRODUCT DESIGN;

SEMICONDUCTOR DEVICES;

EID: 29144453227     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852447     Document Type: Conference Paper

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