Control-aware test architecture design for modular SOC testing

Proceedings of the European Test Workshop

Volumn 2003-January, Issue , 2003, Pages 57-62

  Goel, S K ^a   Marinissen, E J ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Algorithm design and analysis; Bandwidth; Benchmark testing; Circuit testing; Digital integrated circuits; Integrated circuit testing; Laboratories; Pins; Signal design; Wires

Indexed keywords

BANDWIDTH; DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; LABORATORIES; MEMORY ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; SHIFT REGISTERS; SYSTEM-ON-CHIP; WIRE;

ALGORITHM DESIGN AND ANALYSIS; BENCHMARK TESTING; CIRCUIT TESTING; PINS; SIGNAL DESIGN;

INTEGRATED CIRCUIT DESIGN;

EID: 84942856925     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231669     Document Type: Conference Paper

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