Layout-driven SOC test architecture design for test time and wire length minimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 738-743

  Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM PARTITION; COST MODELING; INTEGRATED FASHION; MEMORY DEPTH; RELATIVE WEIGHTS; TEST APPLICATION TIME; TEST ARCHITECTURE; WIRELENGTH MINIMIZATION;

ALGORITHMS; COSTS; DESIGN; EXHIBITIONS; WIRE;

TESTING;

EID: 4544319834     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253695     Document Type: Conference Paper

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