Delay fault testing of core-based systems-on-a-chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 744-749

  Xu, Qiang ^a   Nicolici, Nicola ^a  

^a MCMASTER UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CORE-BASED SOCS; DELAY-FAULT TESTING; DESIGN FOR TEST; MANUFACTURING TESTING; PERFORMANCE VALIDATION; SYSTEMS-ON-A-CHIP; TEST ACCESS MECHANISM; TEST SCHEDULING;

AUTOMATIC TEST PATTERN GENERATION; DESIGN; EXHIBITIONS;

TESTING;

EID: 84893736371     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253696     Document Type: Conference Paper

References (19)

1. J. Aerts and E. J. Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Oct. 1998
2. M. Bushnell and V. Agrawal. Essentials of Electronic Testing. Kluwer Academic Publishers, 2000
3. K. Chakrabarty. Design of System-on-A-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, Montreal, Canada, Apr. 2000
4. L. Chen and S. Dey. DEFUSE: A deterministic functional self-Test methodology for processors. In Proc. IEEE VLSI Test Symposium, pages 255-262, 2000
5. L. Chen, S. Gupta, and M. Breuer. High quality robust tests for path delay faults. In Proc. IEEE VLSI Test Symposium, pages 88-93, 1997
6. I. Ghosh, S. Dey, and N. K. Jha. A fast and low cost testing technique for core-based system-chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(8):863-876, August 2000
7. P.T. Gonciari, B.M. Al-Hashimi, and N. Nicolici. Useless memory allocation in system-on-A-chip test: Problems and solutions. In Proc. IEEE VLSI Test Symposium, pages 423-429, April 2002
8. I. Hamzaoglu and J.H. Patel. Compact two-pattern test set generation for combinational and full scan circuits. In Proc. IEEE International Test Conference, pages 944-953, 1998
9. Y. Huang, W.T. Cheng, C.C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S.M. Reddy. Resource allocation and test scheduling for concurrent test of core based SOC design. In Proc. IEEE Asian Test Symposium, pages 265-270, November 2001
10. V. Iyengar, K. Chakrabarty, and E. Marinissen. Test wrapper and test access mechanism co-optimization for system-onchip. Journal Electronic Testing: Theory and Applications (JETTA), 18:211-228, March 2002
11. V. Iyengar, K. Chakrabarty, and E. Marrinissen. On using rectangle packing for SOC wrapper/TAM co-optimization. In Proc. IEEE VLSI Test Symposium, pages 253-258, 2002
12. W.-C. Lai and K.-T. Cheng. Instruction-level DFT for testing processor and IP cores in system-on-A-chip. In Proc. IEEE/ACM Design Automation Conference (DAC), pages 59-64, 2001
13. H.K. Lee and D.S. Ha. On the generation of test patterns for combinational circuits. Technical Report No. 12-93, Department of Electrical Engineering, Virginia Polytechnic Institute and State University, 1991
14. E.J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Oct. 1998
15. E.J. Marinissen, V. Iyengar, and K. Chakrabarty. ITC02 SOC Test Benchmarks Web Site. http://www.extra.research.philips.com/itc02socbench/.
16. P1500 SECT Task Forces. IEEE P1500 Web Site. http://grouper.ieee.org/ groups/1500/.
17. S. Ravi, G. Lakshminarayana, and N.K. Jha. Testing of core-based systems-on-A-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(3):426-439, March 2001
18. J. Rearick. Too much delay fault coverage is a bad thing. In Proc. IEEE International Test Conference, pages 624-633, November 2001
19. Taiwan Semiconductor Manufacturing Corporation. TSMC 0.18+ CMOS technology. http://www.tsmc.com