Design for consecutive testability of system-on-a-chip with built-in self testable cores

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 487-501

  Yoneda, Tomokazu ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Built in self test; Consecutive testability; Consecutive transparency; Design for testability; System on a chip; Test access mechanism

Indexed keywords

BUILT-IN SELF TEST; INTEGER PROGRAMMING; INTERCONNECTION NETWORKS; LINEAR PROGRAMMING; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; PATTERN RECOGNITION; TIME DOMAIN ANALYSIS; TIMING CIRCUITS;

BUILT-IN SELF TESTABLE CORES; CONSECUTIVE TESTABILITY; CONSECUTIVE TRANSPARENCY; LOGIC FAULTS; SYSTEM-ON-A-CHIP; TEST ACCESS MECHANISM; TEST PATTERN PROPAGATION; TIMING FAULTS;

DESIGN FOR TESTABILITY;

EID: 0036693107     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016553809732     Document Type: Article

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