Low-power RT-level synthesis techniques: A tutorial

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 3, 2005, Pages 333-343

  Pedram, M ^a   Abdollahi, A ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; LOGIC DESIGN; MICROELECTRONICS; OPTIMIZATION; VOLTAGE CONTROL;

INPUT-DISABLING ARCHITECTURE; LOGIC FUNCTIONS; POWER CONSUMPTIONS; SUPPLY VOLTAGES;

POWER ELECTRONICS;

EID: 22944492710     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045111     Document Type: Conference Paper

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