Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1998, Pages 495-498

  Hamada, Mototsugu ^a   Takahashi, Masafumi ^a   Arakida, Hideho ^a   Chiba, Akihiko ^a   Terazawa, Toshihiro ^a   Ishikawa, Takashi ^a   Kanazawa, Masahiro ^a   Igarashi, Mutsunori ^a   Usami, Kimiyoshi ^a   Kuroda, Tadahiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

TOP-DOWN LOW POWER DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 0031634512     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)