Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 6, 2004, Pages 573-589

  Chabini, Noureddine ^a   Wolf, Wayne ^b  

^a ROYAL MILITARY COLLEGE OF CANADA   (Canada)

^b Princeton University   (United States)

Author keywords

CMOS; Combinational digital designs; Dynamic power; Power consumption; Retiming; Sequential digital designs; Supply voltage scaling; Timing constraints

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; ELECTRIC CONVERTERS; ENERGY MANAGEMENT; OPTIMIZATION; PRINTED CIRCUIT DESIGN; THRESHOLD VOLTAGE; TRANSISTORS;

COMBINATIONAL DIGITAL DESIGNS; DYNAMIC POWER; RETIMING; SEQUENTIAL DIGITAL DESIGNS; SUPPLY VOLTAGE SCALING; TIMING CONSTRAINTS;

ELECTRIC POWER UTILIZATION;

EID: 3042661953     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.827569     Document Type: Article

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