Irredundant address bus encoding for low power

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 182-187

  Aghaghiri, Y ^a   Fallah, F ^a   Pedram, M ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACES (COMPUTER); MICROCONTROLLERS; POWER CONTROL; REDUNDANCY; SIGNAL ENCODING; SWITCHING CIRCUITS;

IRREDUNDANT BUS ENCODING; MEMORY ADDRESS BUS;

DATA TRANSFER;

EID: 0034869584     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383128     Document Type: Conference Paper

References (10)

1. Bus-invert coding for low-power I/O
2. Asymptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems
3. Address bus encoding techniques for system level power optimization
4. System-level power optimization of special purpose applications: The beach solution
5. Exploiting the locality of memory references to reduce the address bus energy
6. Bus data coding with zero suppression for low power chip interfaces
7. Low power chip interface based on bus data encoding with adaptive code-book method
8. Power optimization of system-level address buses based on software profiling