Automatic synthesis of low-power gated-clock finite-state machines

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 6, 1996, Pages 630-643

  Benini, Luca ^a   De Micheli, Giovanni ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; FINITE AUTOMATA; OPTIMIZATION; PROBABILITY; TIMING CIRCUITS;

AUTOMATIC SYNTHESIS; CLOCK STOPPING CIRCUITRY; FINITE STATE MACHINE; GATED CLOCKS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030172836     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.503933     Document Type: Article

References (27)

1. M. Alidina and J. Monteiro et al., "Precomputation-hased sequential logic optimization for low power," IEEE Trans. VLSI Syst., vol. 2, pp. 426-436, Jan. 1995.
2. V. Tiwan, S. Malik, and P. Ashar, ''Guarded evaluation: Pushing power management to logic synthesis/design," in Proc. Int. Symp. Low Power Design, Apr. 1995, pp. 221-226.
3. L. Benini, P. Siegel, and G. De Micheli, "Automatic synthesis of gated clocks foi power reduction in sequential circuits," IEEE Design Test Comput., vol. 11, pp. 32-40, Dec. 1994.
4. P.F. Landman and J. M. Rabaey, "Activity-sensitive architectural power analysis for the control path," in Pmc. Int. Symp. Low Power Design. Apr. 1995, pp. 93-98.
5. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in Prnc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 402-407.
6. C. Tsui, M. Pedram, and A. Despain, "Technology decomposition and mapping targeting low power dissipation," in Proc. Design Automation Conf., 1993, pp. 68-73.
7. K. Roy and S. Prasad, "Circuit activity based logic synthesis for low power reliable operations," IEEE Trans. VLSI Syst., vol. 1, pp. 503-513, Dec. 1993.
8. L. Benini and G. De Micheli, "State assignment for low power dissipation," in Proc. IEEE Custom Integrated Circuits Conf., May 1994, pp. 136-139.
9. P. McGeer, J. Sanghavi et al., "ESPRESSO-SIGNATURE: A new exact minimizer for logic functions," IEEE Trans. VLSI Syst., vol. 1, pp. 432-440, Dec. 1993.
10. N. Yeung et al., "The design of a 55SPECin92 RISC processor under 2W," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1994, pp. 206-207.
11. B. Suessmith and G. Paap, III, "Power PC 603 microprocessor power management," Comm. ACM, vol. 37, no. 6. pp. 4316, June 1994.
12. N. Weste and K. Eshragian, Principles of CMOS VLSI Design, 2nd ed. Reading, MA: Addison-Wesley, 1992.
13. K. Trivedi, Probability and Statistics with Reliability, Queuing and Computer Science Applications. Englewood Cliffs, NJ: Prentice-Hall, 1982.
14. G. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Symbolic algorithms to calculate steady-state probabilities of a finite state machine," in Proc. IEEE Euro. Design Test Conf., Feb. 1994, pp. 214-218.
15. _, "Probalistic analysis of large finite state machines," in Proc, Design Automation Conf., June 1994, pp. 270-275.
16. J. Schutz, "A 3.3 V 0.6 μ BiCMOS superscalar microprocessor," in Proc. IEEE Int. Solid-Slats Circuits Conf., Feb. 1994. pp. 202-203.
17. J. Hartmanis and H. Stearns. Algebraic Structure Theory of Dequential Machines. Englewood Cliffs, NJ: Prentic-Hall, 1966.
18. M.R. Garey and D. S. Johnson, Computers and Intractability. A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1983.
19. S. Martello and P. Toth, Knapsack Problems. Algorithms and Computer Implementations. New York: Wiley, 1990.
20. E. Sentovich et al., "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Computer Design, Oct. 1992, pp. 328-333.
21. F. Mailhot and G. De Micheli, "Algorithms for technology mapping based on binary decision dBagrams and on Boolean operations," IEEE Trans. Computer-Aided Design, vol. 12, pp. 599-620, May 1993.
22. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
23. O. Coudert and C. Madre, "Implicit and incremental computation of primes and essential primes of Boolean functions," in Proc, Design Automation Conf., June 1992, pp. 36-39.
24. R. Marcclcscu, D. Marculescu, and M. Pedram, "Switching activity analysis considering spatiotemporal correlations," in Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp. 294-299.
25. J. Monteiro, S. Devadas, and B. Lin, "A methodology for efficient estimation of switching activity in sequential logic circuits," in Proc. Design Automation Conf., June 1994, pp. 315-321.
26. B. Lin and A.R. Newton, "Synthesis of multiple-level logic from symbolic high-level description languages," in Proc. IEEE Int. Conf. Computer Design, Aug. 1989, pp. 187-196.
27. A. Salz and M. Horowitz, "IRSIM: An incremental MOS switch-level simulator,'' in Proc. Design Automation Conf., June 1989, pp. 173-178.