Finite state machine decomposition for low power

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 758-763

  Monteiro, Jose C ^a   Oliveira, Arlindo L ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; FINITE AUTOMATA; PROBABILITY; SEQUENTIAL CIRCUITS; SEQUENTIAL SWITCHING;

CLOCK GATING TECHNIQUES; LOW POWER; SEQUENTIAL LOGIC; SMALL CLUSTERS; STATIONARY STATE PROBABILITY; SWITCHING ACTIVITIES;

COMPUTER CIRCUITS; SEQUENTIAL MACHINES;

FINITE STATE MACHINE (FSM) DECOMPOSITION;

EID: 0031630266     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277235     Document Type: Conference Paper

References (13)

1. M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou. Precomputation-Based Sequential Logic Optimization for Low Power. IEEE Transactions on VLSI Systems, 2(4):426-436, December 1994.
2. L. Benini, P. Siegel, and G. De Micheli. Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines. IEEE Transactions on Computer-Aided Design, 15(6):630-643, June 1996.
3. L. Benini, P. Vuillod, C. Coelho, and G. De Micheli. Synthesis of Low-Power Partially-Clocked Systems from High-Level Specifications. In 9th International Symposium on System Synthesis, November 1996.
4. A. Chandrakasan and R. Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995.
5. S-H. Chow, Y-C. Ho, and T. Hwang. Low Power Realization of Finite State Machines-A Decomposition Approach. ACM Transactions on Design Automation of Electronic Systems, 1(3):315-340, July 1996.
6. S. Devadas and A. Newton. Decomposition and Factorization of Sequential Finite State Machines. IEEE Transactions on Computer-Aided Design, 8(11):1206-1217, November 1989.
7. J. Hartmanis. Symbolic Analysis of a Decomposition of Information Processing. Information Control, 3:154-178, June 1960.
8. B. W. Kemighan and S. Lin. An Efficient Heuristic Procedure for Partitioning Graphs. The Bell System Technical Journal, pages 291-307, February 1970.
9. J. Monteiro, S. Devadas, and A. Ghosh. Retiming Sequential Circuits for Low Power. In Proceedings of the International Conference on Computer-Aided Design, pages 398-402, November 1993.
10. F. Najm. A Survey of Power Estimation Techniques in VLSI Circuits (Invited Paper). IEEE Transactions on VLSI Systems, 2(4):446455, December 1994.
11. A. Papoulis. Probability, Random Variables and Stochastic Processes. McCraw-Hill, Znd edition, 1984.
12. K. Roy and S. Prasad. Circuit Activity Based Logic Synthesis for Low Power Reliable Operations. IEEE Transactions on VLSI Systems, 1(4):503-513, December 1993.
13. C-Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin. Power Estimation Methods for Sequential Logic Circuits. IEEE Transactions on VLSI Systems, 3(3):404-416, September 1995.