A low power scheduling scheme with resources operating at multiple voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 1, 2002, Pages 6-14

  Manzak, Ali ^b   Chakrabarti, Chaitali ^a,c  

^a IEEE   (United States)

^b Lattice Semiconductor Corporation   (United States)

^c Arizona State University   (United States)

Author keywords

Allocation; Data flow graph; Lagrange multiplier method; Low power; Multiple voltages; Resource and latency constraint; Scheduling

Indexed keywords

DATA-FLOW GRAPHS; POWER SCHEDULING;

ALGORITHMS; DATA FLOW ANALYSIS; ELECTRIC POTENTIAL; LAGRANGE MULTIPLIERS; POWER CONTROL; SCHEDULING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036477148     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.988725     Document Type: Article

References (10)

1. Minimizing power consumption in digital CMOS circuits
2. Clustered voltage scaling technique for low power
3. Scheduling with multiple voltages
4. Energy minimization using multiple supply voltages
5. Low power scheduling with resources operating at multiple voltages
6. Datapath scheduling with multiple supply voltages and level conveners
7. Scheduling techniques for variable voltage low power design
8. A 60mW MPEG-4 video codec using clustered voltage scaling with variable supply voltage scheme
9. Variable voltage task scheduling algorithms for minimizing energy