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Volumn 17, Issue , 2004, Pages 670-673

Game theoretic modeling of voltage and frequency scaling during behavioral synthesis

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; FREQUENCY SCALING; NASH EQUILIBRIUM; PORTABLE SYSTEMS;

EID: 2342467983     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (10)
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    • Datapath scheduling with multiple supply voltages and level converters
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    • Datapath scheduling with multiple supply voltages and level converters, "M. Johnson and K. Roy," ACM Trans. on Design Automation of Electronic Systems, vol. 2, no. 3, pp. 227-248, Jul. 1997.
    • (1997) ACM Trans. on Design Automation of Electronic Systems , vol.2 , Issue.3 , pp. 227-248
    • Johnson, M.1    Roy, K.2
  • 3
    • 0036477148 scopus 로고    scopus 로고
    • A low power scheduling scheme with resources operating at multiple voltages
    • Feb.
    • A. Manzak and C. Chakrabarti, "A low power scheduling scheme with resources operating at multiple voltages," IEEE Trans. on Very Large Scale Integrated Systems, vol. 10, no. 1, pp. 6-14, Feb. 2002.
    • (2002) IEEE Trans. on Very Large Scale Integrated Systems , vol.10 , Issue.1 , pp. 6-14
    • Manzak, A.1    Chakrabarti, C.2
  • 7
    • 0000291018 scopus 로고
    • The bargaining problem
    • Apr.
    • J.F. Nash, "The bargaining problem," Econometrica, vol. 18, no. 2, pp. 155-162, Apr. 1950.
    • (1950) Econometrica , vol.18 , Issue.2 , pp. 155-162
    • Nash, J.F.1
  • 8
    • 0029293575 scopus 로고
    • Minimizing power consumption in digital CMOS circuits
    • Apr.
    • A.P. Chandrakasan and R.W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995.
    • (1995) Proceedings of the IEEE , vol.83 , Issue.4 , pp. 498-523
    • Chandrakasan, A.P.1    Brodersen, R.W.2
  • 9
    • 0032138398 scopus 로고    scopus 로고
    • A linear array processor with dynamic frequency clocking for image processing applications
    • Aug.
    • N. Ranganathan, N. Vijaykrishnan and N. Bhavanishankar, "A linear array processor with dynamic frequency clocking for image processing applications," IEEE Trans. on CSVT, vol. 8, no. 4, pp. 435-445, Aug. 1998.
    • (1998) IEEE Trans. on CSVT , vol.8 , Issue.4 , pp. 435-445
    • Ranganathan, N.1    Vijaykrishnan, N.2    Bhavanishankar, N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.