Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 153-158

  Chuang, C T ^a   Joshi, R V ^a   Puri, R ^a   Kim, K ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; IMPACT IONIZATION; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; NETWORKS (CIRCUITS); RADIATION HARDENING;

CIRCUIT DESIGNS; DESIGN CHALLENGES; DESIGN CONSIDERATIONS; DIGITAL APPLICATIONS; PARTIALLY DEPLETED SOI; SOFT ERROR RATE; STRAINED SI CHANNEL; TUNNELING CURRENT;

DESIGN;

EID: 1242340064     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194724     Document Type: Conference Paper

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