Online BIST and BIST-based diagnosis of FPGA logic blocks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 12, 2004, Pages 1284-1294

  Abramovici, Miron ^a   Stroud, Charles E ^b   Emmert, John M ^c  

^a Design Automation for Flexible Chip Architectures (DAFCA)   (United States)

^b AUBURN UNIVERSITY   (United States)

^c University of North Carolina at Charlotte   (United States)

Author keywords

Adaptive computing; Built in self test (BIST); Fault diagnosis; Fault tolerance; Field programmable gate arrays (FPGAs); Online testing

Indexed keywords

ADAPTIVE SYSTEMS; ENCODING (SYMBOLS); FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; ONLINE SYSTEMS; SET THEORY;

ADAPTIVE COMPUTING; BUILT-IN SELF-TEST (BIST); FAULT DIAGNOSIS; ONLINE TESTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 12344302272     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.837989     Document Type: Article

References (33)

1. W. Huang and F. Lombardi, "An approach to testing programmable/configurable field programmable gate arrays," in Proc. IEEE VLSI Test Symp., 1996, pp. 450-455.
2. W. Huang, F. Meyer, X. Chen. and F. Lombardi, "Testing configurable LUT-based FPGAs," IEEE Trans. VLSI Syst., vol. 6, pp. 276-283, Apr. 1998.
3. T. Inoue, S. Miyazaki, and H. Fujiwara, "Universal fault diagnosis for lookup table FPGAs," IEEE Des. Test Comput., vol. 15, pp. 39-44, Jan. 1998.
4. C. Jordan and W. P. Marnane, "Incoming inspection of FPGAs," in Proc. European Test Conf., 1993, pp. 371-377.
5. F. Lombardi, D. Ashen, X. Chen, and W. Huang, "Diagnosing programmable interconnect systems for FPGAs," in Proc. ACM Int. Symp. FPGAs, 1996, pp. 100-106.
6. M. Renovell, J. Figueras, and Y. Zorian, "Test of RAM-based FPGA: methodology and application to interconnects," in Proc. IEEE VLSI Test Symp., 1997, pp. 230-237.
7. M. Renovell, J. Portal, J. Figueras, and Y. Zorian, "Testing the interconnect of RAM-based FPGAs," IEEE Des. Test Comput., vol. 15, pp. 45-50, Jan. 1998.
8. _, "SRAM-based FPGA: Testing the LUT/RAM modules," in Proc. IEEE Int. Test Conf., 1998, pp. 1102-1111.
9. _, "SRAM-based FPGA: testing the embedded RAM modules," J. Electron Testing: Theory Applicat., vol. 14, no. 1/2, pp. 159-167, 1999.
10. B. Culbertson, R. Amerson, R. Carter, P. Kuekes, and G. Snider, "Defect tolerance on the Teramac custom computer," in Proc. IEEE Symp. Field-Programmable Custom Computing Machines, 1997, pp. 116-123.
11. C. Hamilton, G. Gibson, S. Wijesuriya, and C. Stroud, "Enhanced BIST-based diagnosis of FPGAs via boundary scan access," in Proc. IEEE VLSI Test Symp., 1999, pp. 413-418.
12. C. Stroud, P. Chen, S. Konala, and M. Abramovici, "Evaluation of FPGA resources for built-in self-test of programmable logic blocks," in Proc. ACM Int. Symp. FPGAs, 1996, pp. 107-113.
13. C. Stroud, S. Konala, P. Chen, and M. Abramovici, "Built-in self-test for programmable logic blocks in FPGAs," in Proc. IEEE VLSI Test Symp., 1996, pp. 387-392.
14. C. Stroud, E. Lee, S. Konala, and M. Abramovici, "Using ILA testing for BIST in FPGAs," in Proc. IEEE Int. Test Conf., 1996, pp. 68-75.
15. C. Stroud, E. Lee, and M. Abramovici, "BIST-based diagnostics for FPGA logic blocks," in Proc. IEEE Int. Test Conf., 1997, pp. 539-547.
16. C. Stroud, S. Wijesuriya, C. Hamilton, and M. Abramovici, "Built-in self-test of FPGA interconnect," in Proc. IEEE Int. Test Conf., 1998, pp. 404-411.
17. S.-J. Wang and T.-M. Tsai, "Test and diagnosis of faulty logic blocks in FPGAs," in Proc. IEEE Int. Conf. Computer-Aided Design, 1997, pp. 722-727.
18. A. Burress and P. Lala, "Online testable logic design for FPGA implementation," in Proc. IEEE Int. Test Conf., 1997, pp. 471-478.
19. C. Zeng, N. Saxena, and E. McCluskey, "Finite state machine synthesis with concurrent error detection," in Proc. IEEE Int. Test Conf., 1999, pp. 672-679.
20. N. Shnidman, W. Mangione-Smith, and M. Potkonjak, "Online fault detection for bus-based field programmable gate arrays," IEEE Trans. VLSI Syst., vol. 6, pp. 656-666, Dec. 1998.
21. A. Steininger and C. Scherrer, "On the necessity of online BIST in safety critical applications," in Proc. Fault-Tolerant Computing Symp., 1999, pp. 208-215.
22. M. Abramovici, C. Stroud, S. Wijesuriya, C. Hamilton, and V. Verma, "Using roving STARs for online testing and diagnosis of FPGAs in fault-tolerant applications," in Proc. Int. Test Conf., 1999, pp. 973-982.
23. M. Abramovici, J. Emmert, and C. Stroud, "Roving STARs: An integrated approach to online testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems," in Proc. NASA/DoD Workshop on Evolvable Hardware, 2001, pp. 73-92.
24. M. Abramovici and C. Stroud, "BIST-based delay-fault testing in FPGAs," in Proc. IEEE Int. Online Test Workshop, 2002, pp. 131-134.
25. Lattice Semiconductor Available. [Online] http://www.latticesemi.com/products
26. D. Siewiorek and R. Swarz, The Theory and Practice of Reliable System Design. Bedford, MA: Digital Press, 1982.
27. J. Emmert, C. Stroud, B. Skaggs, and M. Abramovici, "Dynamic fault tolerance in FPGAs via partial reconfiguration," in Proc. IEEE Symp. Field-Programmable Custom Computing Machines, 2000, pp. 165-174.
28. C. Stroud, M. Lashinsky, J. Nail, J. Emmert, and M. Abramovici, "Online BIST and diagnosis of FPGA interconnect using roving STARs," in Proc. IEEE Int. OnLine Test Workshop, 2001, pp. 31-39.
29. M. Abramovici and C. Stroud, "BIST-based test and diagnosis of FPGA logic blocks," IEEE Trans. VLSI Syst., vol. 9, pp. 159-172, Apr. 2001.
30. C. Stroud, A Designer's Guide to Built-in Self-Test. Norwell, MA: Kluwer, 2002.
31. Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard P1149.1-1990, 1990.
32. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Piscataway, NJ: IEEE Press, 1994.
33. Xilinx, Inc. [Online]. Available: http://www.xilinx.com/products