Universal fault diagnosis for lookup table FPGAs

IEEE Design and Test of Computers

Volumn 15, Issue 1, 1998, Pages 39-44

  Inoue, Tomoo ^a,b,c   Miyazaki, Satoshi ^a,d,e   Fujiwara, Hideo ^a,c,f,g,h  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b MEIJI UNIVERSITY   (Japan)

^c IEEE

^d SHARP CORPORATION   (Japan)

^e OKAYAMA UNIVERSITY   (Japan)

^f OSAKA UNIVERSITY   (Japan)

^g Institute of Electronics   (Japan)

^h IPSJ   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; ERROR DETECTION; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; TABLE LOOKUP;

CONFIGURABLE LOGIC BLOCKS (CLB); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); UNIVERSAL FAULT DIAGNOSIS PROCEDURE;

LOGIC GATES;

EID: 0031655580     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.655181     Document Type: Article

References (7)

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4. H. Michinishi et al., "A Test Methodology for Configurable Logic Blocks of Lookup Table Based FPGAs," IEICE Trans. D-I, Vol. J79-D-I, No. 12, Dec. 1996, pp. 1141-1150 (in Japanese).
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6. T. Inoue, S. Miyazaki, and H. Fujiwara, "On the Complexity of Universal Fault Diagnosis for Lookup Table FPGAs," Tech. Report NAIST-IS-TR97020, Graduate School of Information Science, Nara Institute of Science and Technology, 1997 (http://isw3.aist-nara.ac.jp/IS/TechReport2/report/97020.ps).
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