Testing configurable LUT-based FPGA's

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 2, 1998, Pages 276-283

  Huang, Wei Kang ^b   Meyer, Fred J ^a,c   Chen, Xiao Tao ^d   Lombardi, Fabrizio ^a,c  

^a IEEE

^b FUDAN UNIVERSITY   (China)

^c TEXAS A AND M UNIVERSITY   (United States)

^d NOKIA RESEARCH CENTER   (United States)

Author keywords

C testability; Field programmable gate array; Programmability; Reconfigurability; Testing

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; LOGIC CIRCUITS; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES;

EID: 0032099764     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.678888     Document Type: Article

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