Built-in self-test of logic blocks in FPGAs (finally, a free lunch: BIST without overhead!)

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 387-392

  Stroud, Charles ^a   Konala, Srinivasa ^a   Chen, Ping ^a   Abramovici, Miron ^a  

^a UNIVERSITY OF KENTUCKY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; RANDOM ACCESS STORAGE;

BUILT IN SELF TEST; FIELD PROGRAMMABLE GATE ARRAY; MAXIMAL FAULT COVERAGE; OPTIMIZED RECONFIGURABLE CELL ARRAY; PROGRAMMABLE LOGIC BLOCKS;

INTEGRATED CIRCUIT TESTING;

EID: 0029700620     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)