BIST-based test and diagnosis of FPGA logic blocks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 1, 2001, Pages 159-172

  Abramovici, Miron ^a,b   Stroud, Charles E ^a,c,d  

^a IEEE   (United States)

^b NOKIA RESEARCH CENTER   (United States)

^c UNIVERSITY OF KENTUCKY   (United States)

^d University of North Carolina at Charlotte   (United States)

Author keywords

Built in self test; Fault tolerance; FPGA diagnosis; FPGA testing; Reconfigurable systems

Indexed keywords

FAULT TOLERANCE; PROGRAMMABLE LOGIC BLOCKS; RECONFIGURABLE SYSTEMS;

DESIGN FOR TESTABILITY; FIELD PROGRAMMABLE GATE ARRAYS; FITS AND TOLERANCES; INTEGRATED CIRCUIT TESTING; LOGIC DEVICES; MULTIPLEXING EQUIPMENT; PROGRAMMABLE LOGIC CONTROLLERS;

BUILT-IN SELF TEST;

EID: 0035242889     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.920830     Document Type: Article

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