-
2
-
-
0029732376
-
Field testing for cosmic ray soft errors in semiconductor memories
-
T. J. O'Gorman, J. M. Ross, A. H. Taber, J. F. Ziegler, H. P. Muhlfeld, C. J. Montrose, H. W. Curtis, and J. L. Walsh, "Field testing for cosmic ray soft errors in semiconductor memories," IBM J. Res., Develop., vol. 40, pp. pp. 41-50, 1996.
-
(1996)
IBM J. Res., Develop.
, vol.40
, pp. 41-50
-
-
O'Gorman, T.J.1
Ross, J.M.2
Taber, A.H.3
Ziegler, J.F.4
Muhlfeld, H.P.5
Montrose, C.J.6
Curtis, H.W.7
Walsh, J.L.8
-
3
-
-
33747799245
-
Architecture issues and solutions for a high-capacity FPGA
-
Monterey, CA
-
S. Trimberger, K. Doung, and B. Conn, "Architecture issues and solutions for a high-capacity FPGA," in Proc. FPGA'97, Monterey, CA, 1997.
-
(1997)
Proc. FPGA'97
-
-
Trimberger, S.1
Doung, K.2
Conn, B.3
-
4
-
-
0025505369
-
Architectures of field-programmable gate arrays: The effect of logic block functionality on area efficiency
-
J. Rose, R. Francis, and P. Chow, "Architectures of field-programmable gate arrays: The effect of logic block functionality on area efficiency," IEEE J. Solid-State Circuits, pp. 1217-1225, 1990.
-
(1990)
IEEE J. Solid-State Circuits
, pp. 1217-1225
-
-
Rose, J.1
Francis, R.2
Chow, P.3
-
5
-
-
0007438643
-
-
San Jose, CA: Altera
-
Altera, Data Book. San Jose, CA: Altera, 1996.
-
(1996)
Data Book
-
-
-
6
-
-
0029518340
-
Advanced technologies for a command and data handling subsystem in a 'better, faster, cheaper' environment
-
Cambridge, MA
-
K. W. Bernhardt, "Advanced technologies for a command and data handling subsystem in a 'better, faster, cheaper' environment," in Proc. Digital Avionics Systems Conf., Cambridge, MA, 1995.
-
(1995)
Proc. Digital Avionics Systems Conf.
-
-
Bernhardt, K.W.1
-
7
-
-
0020811741
-
Functional testing of semiconductor random access memories
-
M. S. Abadir and H. Reghbati, "Functional testing of semiconductor random access memories," Comput. Surv., vol. 15, pp. 175-198, 1983.
-
(1983)
Comput. Surv.
, vol.15
, pp. 175-198
-
-
Abadir, M.S.1
Reghbati, H.2
-
10
-
-
0015986205
-
On modifying logic networks to improve their diagnosability
-
Jan.
-
J. P. Hayes, "On modifying logic networks to improve their diagnosability," IEEE Trans. Comput., vol. C-23, pp. 56-62, Jan. 1974.
-
(1974)
IEEE Trans. Comput.
, vol.C-23
, pp. 56-62
-
-
Hayes, J.P.1
-
11
-
-
85160551624
-
A study of the data communication problems in self-repairable multiprocessors
-
Washington, DC: Thompson
-
K. N. Levitt, M. W. Green, and J. Goldberg, "A study of the data communication problems in self-repairable multiprocessors," in Proc. Conf. AFIPS, vol. 32. Washington, DC: Thompson, 1968, pp. 515-527.
-
(1968)
Proc. Conf. AFIPS
, vol.32
, pp. 515-527
-
-
Levitt, K.N.1
Green, M.W.2
Goldberg, J.3
-
12
-
-
0027610022
-
A tutorial on built-in self-test
-
V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A tutorial on built-in self-test," IEEE Design, Test of Comput., Mag. vol. 10, 1993, pp. 69-77.
-
(1993)
IEEE Design, Test of Comput., Mag.
, vol.10
, pp. 69-77
-
-
Agrawal, V.D.1
Kime, C.R.2
Saluja, K.K.3
-
13
-
-
0029700620
-
Built-in self-test of logic blocks in FPGA's (finally, a free lunch: BIST without overhead!)
-
C. Stroud, S. Konala, P. Chen, and M. Ambramovici, "Built-in self-test of logic blocks in FPGA's (finally, a free lunch: BIST without overhead!)," in Proc. IEEE VLSI Test Symp., 1996.
-
(1996)
Proc. IEEE VLSI Test Symp.
-
-
Stroud, C.1
Konala, S.2
Chen, P.3
Ambramovici, M.4
-
14
-
-
0029700925
-
An approach for testing programmable/configurable field programmable gate arrays
-
W. K. Huang and F. Lombardi, "An approach for testing programmable/configurable field programmable gate arrays," in Proc. IEEE VLSI Test Symp., 1996.
-
(1996)
Proc. IEEE VLSI Test Symp.
-
-
Huang, W.K.1
Lombardi, F.2
-
15
-
-
0030411716
-
A test methodology for interconnect structures of LUT-based FPGA's
-
H. Michinishi et al., "A test methodology for interconnect structures of LUT-based FPGA's," in Proc. Asian Test Symp., 1996.
-
(1996)
Proc. Asian Test Symp.
-
-
Michinishi, H.1
-
16
-
-
0029519091
-
Universal test complexity of field-programmable gate arrays
-
T. Inoue et al., "Universal test complexity of field-programmable gate arrays," in Proc. Asian Test Symp., 1995.
-
(1995)
Proc. Asian Test Symp.
-
-
Inoue, T.1
-
17
-
-
0029490526
-
A row-based FPGA for single and multiple stuck-at fault detection
-
X. T. Chen, W. K. Huang, F. Lombardi, and X. Sun, "A row-based FPGA for single and multiple stuck-at fault detection," in Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Syst., 1995.
-
(1995)
Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Syst.
-
-
Chen, X.T.1
Huang, W.K.2
Lombardi, F.3
Sun, X.4
-
19
-
-
0029406749
-
Effects of technology mapping on fault-detection coverage in reprogrammable FPGA's
-
K. Kwiat, W. Debany, and S. Hariri, "Effects of technology mapping on fault-detection coverage in reprogrammable FPGA's," Inst. Elect. Eng.: Comput., Digital Tech., 1995.
-
(1995)
Inst. Elect. Eng.: Comput., Digital Tech.
-
-
Kwiat, K.1
Debany, W.2
Hariri, S.3
-
21
-
-
33747752788
-
Reconfigurable logic for fault tolerance
-
Oxford, U.K.: Oxford University Press
-
R. Cuddapah and M. Corba, "Reconfigurable logic for fault tolerance," in Field Programmable Logic and Applications. Oxford, U.K.: Oxford University Press, 1995.
-
(1995)
Field Programmable Logic and Applications
-
-
Cuddapah, R.1
Corba, M.2
-
22
-
-
0029713590
-
Node-covering based defect and fault-tolerance methods for increased yield in FPGA's
-
F. Hanchek and S. Dutt, "Node-covering based defect and fault-tolerance methods for increased yield in FPGA's," in Proc. 9th Int. Conf. VLSI Design, 1995, pp. 225-229.
-
(1995)
Proc. 9th Int. Conf. VLSI Design
, pp. 225-229
-
-
Hanchek, F.1
Dutt, S.2
-
23
-
-
0028397566
-
The yield enhancement of field-programmable gate arrays
-
N. J. Howard et al., "The yield enhancement of field-programmable gate arrays," IEEE Trans. VLSI Syst., vol. 2, pp. 115-123, 1994.
-
(1994)
IEEE Trans. VLSI Syst.
, vol.2
, pp. 115-123
-
-
Howard, N.J.1
-
24
-
-
0000484585
-
On routability for FPGA's under faulty conditions
-
K. Roy and S. Nag, "On routability for FPGA's under faulty conditions," IEEE Trans. Comput., vol. 44, pp. 1296-1305, 1996.
-
(1996)
IEEE Trans. Comput.
, vol.44
, pp. 1296-1305
-
-
Roy, K.1
Nag, S.2
-
26
-
-
0030169878
-
An experimental survey of heavy ion induced dielectric rupture in actel field programmable gate arrays (FPGA's)
-
G. Swift and R. Katz, "An experimental survey of heavy ion induced dielectric rupture in actel field programmable gate arrays (FPGA's)," IEEE Trans. Nucl. Sci., vol. 43, pp. 967-972, 1996.
-
(1996)
IEEE Trans. Nucl. Sci.
, vol.43
, pp. 967-972
-
-
Swift, G.1
Katz, R.2
-
27
-
-
0028714150
-
Single event effect proton and heavy ion test results for candidate spacecraft electronics
-
K. A. LaBel et al., "Single event effect proton and heavy ion test results for candidate spacecraft electronics," in Proc. IEEE Radiation Effects Data Workshop, 1994.
-
(1994)
Proc. IEEE Radiation Effects Data Workshop
-
-
LaBel, K.A.1
-
28
-
-
0023209043
-
Using redundancy for concurrent testing and repairing of systolic arrays
-
Pittsburgh, PA
-
L. A. Shombert and D. P. Siewiorek, "Using redundancy for concurrent testing and repairing of systolic arrays," presented at FTCS-17, Pittsburgh, PA, 1987.
-
(1987)
FTCS-17
-
-
Shombert, L.A.1
Siewiorek, D.P.2
-
29
-
-
0032096706
-
Low overhead fault-tolerant FPGA systems
-
J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Low overhead fault-tolerant FPGA systems," IEEE Trans. VLSI, vol. 6, 1998.
-
(1998)
IEEE Trans. VLSI
, vol.6
-
-
Lach, J.1
Mangione-Smith, W.H.2
Potkonjak, M.3
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