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Volumn 2000-January, Issue , 2000, Pages 165-174

Dynamic fault tolerance in FPGAs via partial reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; DYNAMIC MODELS; FAULT DETECTION; FAULT TOLERANCE; RECONFIGURABLE HARDWARE; STARS; TRANSFER FUNCTIONS;

EID: 84889958959     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903403     Document Type: Conference Paper
Times cited : (85)

References (20)
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    • Zeng, C.1    Saxena, N.2    McCluskey, E.J.3
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    • On the necessity of on-line BIST in safety critical applications
    • A. Steininger and Scherrer, "On the Necessity of On-Line BIST in Safety Critical Applications", Proc 29th Fault-Tolerant Computing Symp", pp. 208-215, 1999.
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    • Steininger, A.1    Scherrer2
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    • Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements
    • August
    • J. Narasimhan, K. Nakajima, C. Rim, and A. Daubura, "Yield Enhancement of Programmable ASIC Arrays by Reconfiguration of Circuit Placements", IEEE Trans, on CAD, Vol. 13, No. 8, pp. 976-986, August 1994.
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    • Narasimhan, J.1    Nakajima, K.2    Rim, C.3    Daubura, A.4
  • 12
    • 0028397566 scopus 로고
    • The yield enhancement of field programmable gate arrays
    • N. Howard, A. Tyrrell, and N. P. Allinson, "The Yield Enhancement of Field Programmable Gate Arrays", IEEE Trans, on VLSI Systems, Vol. 2, pp. 115-123, 1994.
    • (1994) IEEE Trans, on VLSI Systems , vol.2 , pp. 115-123
    • Howard, N.1    Tyrrell, A.2    Allinson, N.P.3
  • 13
    • 33746031652 scopus 로고
    • A novel approach to defect tolerant design for SRAM based FPGAs
    • J. Kelly and P. Ivey, "A Novel Approach to Defect Tolerant Design for SRAM Based FPGAs", Proc. ACM Int'l Workshop on FPGAs, pp. 7-11, 1994.
    • (1994) Proc. ACM Int'l Workshop on FPGAs , pp. 7-11
    • Kelly, J.1    Ivey, P.2
  • 15
    • 0031649068 scopus 로고    scopus 로고
    • Methodologies for tolerating logic and interconnect faults in FPGAs
    • Jan.
    • F. Hanchek and S. Dutt, "Methodologies for Tolerating Logic and Interconnect Faults in FPGAs", IEEE Trans, on Computers, pp. 15-33, Jan. 1998.
    • (1998) IEEE Trans, on Computers , pp. 15-33
    • Hanchek, F.1    Dutt, S.2
  • 16
    • 0031099007 scopus 로고    scopus 로고
    • REMOD: A new methodology for designing fault-tolerant arithmetic circuits
    • S. Dutt and F. Hanchek, "REMOD: A New Methodology for Designing Fault-Tolerant Arithmetic Circuits", IEEE Trans. on VLSI Systems, Vol. 5, pp. 34-56, 1997.
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    • Efficient network flow based technique for dynamic fault reconfiguration in FPGAs
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    • Reconfiguring FPGA mapped designs with applications to fault tolerance and reconfigurable computing
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.