SRAM-based FPGA's: Testing the LUT/RAM modules

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 1102-1111

  Renovell, M ^a   Portal, J M ^a   Figueras, J ^a   Zorian, Y ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; SHIFT REGISTERS;

CONFIGURABLE LOGICS;

INTEGRATED CIRCUIT TESTING;

EID: 0032315258     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)