Independently driven DG MOSFETs for mixed-signal circuits: Part I - Quasi-static and nonquasi-static channel coupling

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 2086-2093

  Pei, Gen ^a   Kan, Edwin Chih Chuan ^a  

^a Cornell University   (United States)

Author keywords

Capacitance network; Channel coupling; Double gate (DG) MOSFET; Mixed signal circuits; Nonquasi static modeling; Quasi static modeling

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; COUPLED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; GATES (TRANSISTOR); LITHOGRAPHY; MATHEMATICAL MODELS; MIXER CIRCUITS; NATURAL FREQUENCIES; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

CAPACITANCE NETWORK; CHANNEL COUPLING; DOUBLE GATE MOSFET; MIXED SIGNAL CIRCUITS; NONQUASI STATIC MODELING; QUASI STATIC MODELING;

MOSFET DEVICES;

EID: 10644271735     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.838338     Document Type: Article

References (35)

1. K. H. Yuen, T. Y. Man, A. C. K. Chan, and M. Chan, "A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure," IEEE Electron Device Lett., vol. 24, pp. 518-520, Aug. 2003.
2. C. Kuo, T.-J. King, and C. Hu, "A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications," IEEE Trans. Electron Devices, vol. 50, pp. 2408-2416, Dec. 2003.
3. L. Wei, Z. Chen, and K. Roy, "Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs," in Proc. IEEE Int. SOI Conf., 1997, pp. 82-83.
4. P. Beckett, "Fine-grained reconfigurable logic array based on double gate transistors," in Proc. IEEE Int. FPT Conf., 2002, pp. 260-267.
5. T. Cakici, A. Bansal, and K. Roy, "A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices," in Proc. IEEE Int. SOI Conf., 2003, pp. 21-22.
6. K. W. Guarini, P. M. Solomon, Y. Zhang, K. K. Chan, E. C. Jones, G. M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, C. Cabral, Jr., C. Lavoie, V. Ku, D. C. Boyd, K. S. Petrarca, I. V. Babich, J. Treichler, and P. M. Kozlowski, "Triple-self-aligned, planar double-gate MOSFETs: devices and circuits," in IEDM Tech. Dig., 2001, pp. 425-428.
7. S. Mitra, A. Salman, D. P. Ioannou, and D. E. Ioannou, "LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load," in Proc. IEEE Int. SOI Conf., 2002, pp. 66-67.
8. S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, and D. E. Ioannou, " Low voltage/low power sub 50 nm double gate SOI ratioed logic," in Proc. IEEE Int. SOI Conf., 2003, pp. 177-178.
9. G. Pei and E. C. Kan, "Circuit design principles for independently driven double-gate MOSFETs," in Proc. Si NanoElectronics Workshop 2002, pp. 29-30.
10. G. Pei and E. C. Kan, "Independently driven double-gate MOSFET for mixed-signal circuits," in Proc. Techcon 2003, 2003, p. 178.
11. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861-2869, Dec. 2001.
12. P. M. Solomon, "Mixed mode double-gate FET model," in Proc. DRC Tech. Dig., 2001, pp. 77-78.
13. G. Pei, W. Ni, A. V. Kammula, B. A. Minch, and E. C. Kan, "A physical compact model of DGMOSFET for mixed-signal circuit applications, part I: model description," IEEE Trans. Electron Devices, vol. 50, pp. 2135-2143, Oct. 2003.
14. Y. Taur, X. Liang, W. Wang, and H. Lu, "A continuous, analytic drain-current model for DG MOSFETs," IEEE Electron Device Lett., vol. 25, pp. 107-109, Feb. 2004.
15. S. Zhang, X. Lin, R. Huang, R. Han, and M. Chan, "A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application," IEEE Trans. Electron Devices, vol. 50, pp. 2297-2300, Nov. 2003.
16. D. M. Fried, J. S. Duster, and K. T. Kornegay, "Improved independent gate N-type FinFET fabrication and characterization," IEEE Electron Device Lett., vol. 24, pp. 592-594, Sept. 2003.
17. Z. Ren, R. Venugopal, S. Datta, and M. Lundstrom, "Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Greens function simulation," in IEDM Tech. Dig., 2001, pp. 107-110.
18. Atlas User's Manual-Device Simulation Software, SILVACO International Inc., Santa Clara, CA, 2000.
19. D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in Proc. VLSI Circuits Symp., 1999, pp. 171-172.
20. S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984.
21. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Computer-Aided Design, vol. 7, pp. 1164-1171, Nov. 1988.
22. N. Arora, MOSFET Models for VLSI Circuit Simulation. New York: Springer-Verlag, 1993.
23. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.
24. K. Kim and J. G. Fossum, "Double-gate CMOS: symmetrical-versus asymmetrical-gate device," IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
25. G. Tsutsui, T. Nagumo, and T. Hiramoto, "Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs," IEEE Trans. Nanotechnol., vol. 2, pp. 314-318, Dec. 2003.
26. 2 interface of a MOSFET," Solid State Electron., vol. 37, no. 10, pp. 839-849, 1989.
27. B. Majkusiak, T. Janik, and J. Walczak, "Semiconductor thickness effects in the double-gate SOI MOSFET," IEEE Trans. Electron Devices vol. 45, pp. 1127-1134, May 1998.
28. R. T. Howe and C. G. Sodini, Microelectronics: An Integrated Approach Englewood Cliffs, NJ: Prentice-Hall, 1997.
29. M. Ieong, H.-S. P. Wong, Y. Taur, P. Oldiges, and D. J. Frank, "DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS," in Proc. SISPAD, 2000, pp. 147-150.
30. L. Ge and J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs," IEEE Trans. Electron Devices vol. 49, pp. 287-294, Feb. 2002.
31. G. A. Kathawala, B. Winstead, and U. Ravaioli, "Monte Carlo simulations of double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 2467-2473, Dec. 2003.
32. J. Maget, M. Tiebout, and R. Kraus, "Influence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 37, pp. 953-958, July 2002.
33. K. Shen, F. P. S. Hui, W. M. Y. Wong, Z. Chen, J. Lau, P. C. H. Chan, and P. K. Ko, "A three-terminal SOI gated varactor for RF applications," IEEE Trans. Electron Devices, vol. 48, pp. 289-293, Feb. 2001.
34. W. M. Y. Wong, P. S. Hui, Z. Chen, K. Shen, J. Lau, P. C. H. Chan, and P. K. Ko, "A wide tuning range gated varactor," IEEE J. Solid-State Circuits, vol. 35, pp. 773-779, May 2000.
35. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.