Low Voltage / Low Power sub 50 nm Double Gate SOI Ratioed Logic

IEEE International SOI Conference

Volumn , Issue , 2003, Pages 177-178

  Mitra, Souvick ^a   Salman, Akram ^b   Ioannou, Dimitris P ^a   Tretz, Christophe ^c   Ioannou, Dimitris E ^a  

^a GEORGE MASON UNIVERSITY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; LOGIC GATES; MOSFET DEVICES;

CHANNEL LENGTHS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0142185837     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2003.1242942     Document Type: Conference Paper

References (5)

1. ITRS 2002;
2. P. M. Solomon et al., IEEE Circuits and Dev., p. 48 (2003);
3. K. Kim and J. G. Fossum, IEEEE-D 48, p. 294 (2001),
4. S. Mitra et al., IEEE Intl. SOI Conf, p. 66 (2002);
5. Silvaco Corp., Santa Clara, CA.