A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications

IEEE Transactions on Electron Devices

Volumn 50, Issue 12, 2003, Pages 2408-2416

  Kuo, Charles ^a   King, Tsu Jae ^b   Hu, Chenming ^b,c  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Double gate MOSFETs; DRAM; Floating body DRAM; Fully depleted; Scaled CMOS; Thin body SOI

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTING FILMS; SEMICONDUCTOR DOPING; SIGNAL PROCESSING; THRESHOLD VOLTAGE;

BODY EFFECT CHANNEL CONDUCTIVITY; CELL GEOMETRY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0347338041     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.819257     Document Type: Article

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