A Self-Aligned, Electrically Separable Double-Gate MOS Transistor Technology for Dynamic Threshold Voltage Application

IEEE Transactions on Electron Devices

Volumn 50, Issue 11, 2003, Pages 2297-2300

  Zhang, Shengdong ^a   Lin, Xinnan ^b   Huang, Ru ^a   Han, Ruqi ^a   Chan, Mansun ^b  

^a PEKING UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Dynamic threshold; Electrically separable double gate; MOS transistor; Self aligned structure; Voltage

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); GRAIN SIZE AND SHAPE; IMAGING TECHNIQUES; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON; THRESHOLD VOLTAGE;

DEVICE STRUCTURE;

MOSFET DEVICES;

EID: 0242364167     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.818598     Document Type: Article

References (10)

1. D. Frank, S. Laux, and M. Fischetti, "Monte Carlo simulation of a 30-nm dual-gate MOSFET: How far can silicon go?," in IEDM Tech. Dig., 1992, p. 553.
2. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance," IEEE Electron Device Lett., vol. EDL-8, pp. 410-412, 1987.
3. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,'' IEEE Trans. Electron Devices, vol. 48, pp. 2861-2869, Dec. 2001.
4. I. Yang, C. Vieri, A. Chandraksan, and D. A.Dimitri A. Antoniadis, "Bottom-gate CMOS on SOIAS for dynamic threshold voltage control," IEEE. Trans. Electron Devices, vol. 44, pp. 822-831, 1997.
5. H.-S. Wong, K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in IEDM Tech. Dig., 1997, pp. 427-430.
6. D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Andersen, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, "A folded-channel MOSFET for deep-sub-tenth micron era," in IEDM Tech. Dig., 1998, pp. 1032-1034.
7. X. Huang, W.-C. Lee, C. Ku, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS," in IEDM Tech. Dig., 1999. pp. 67-70.
8. J. H. Lee, G. Tarashi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D. A. Antoniadis, "Super self-aligned double-gate (SSDG) MOSFET's utilizing oxidation rate difference and selective epitaxy," in IEDM Tech. Dig., 1999, pp. 71-74.
9. H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang, and P. K. Ko, "Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method," IEEE Trans. Electron Devices, vol. 47, pp. 1580-1586, Aug. 2000.
10. J. P. Colinge, ULSI Devices. New York: Wiley, 2000, pp. 234-235.