LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 66-67

  Mitra, Souvick ^a   Salman, Akram ^a   Ioannou, Dimitris P ^a   Ioannou, Dimitris E ^a  

^a GEORGE MASON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; LOGIC GATES; POLYSILICON; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

STATIC POWER DISSIPATION;

MOSFET DEVICES;

EID: 0036901928     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044419     Document Type: Conference Paper

References (5)

1. J. Kedzierski et al., IEDM'01, p.437.
2. K. Kim and J.G. Fossum, IEEE-ED 48, p.294 (2001).
3. N. Subba et al., 2000 IEEE Intern. SOI Conf., p.26.
4. Silvaco Corp., Santa Clara, CA.
5. R. Zhang and K. Roy, IEEE-ED 49, p.852 (2002). * Funded by NSF grant #ECS-9900464.